71M6533G Maxim, 71M6533G Datasheet
71M6533G
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71M6533G Summary of contents
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... RAM, and 128KB (71M6533/H, 71M6534), or 256KB (71M6533G, 71M6534H) flash, which can be programmed in the field with new code and/or data during meter operation. Higher processing and sampling rates and larger memory offer a powerful metering platform for commercial and industrial meters with up to class 0 ...
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Hardware Description .................................................................................................................... 9 1.1 Hardware Overview ............................................................................................................... 9 1.2 Analog Front End (AFE) ........................................................................................................ 9 1.2.1 Signal Input Pins ......................................................................................................... 9 1.2.2 Input Multiplexer ........................................................................................................ 10 1.2.3 A/D Converter (ADC) ................................................................................................. 11 1.2.4 FIR Filter ................................................................................................................... 11 1.2.5 ...
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... Wake on Timer .......................................................................................................... 66 2.6 Data Flow ............................................................................................................................. 66 2.7 CE/MPU Communication .................................................................................................... 67 3 Application Information ............................................................................................................... 68 3.1 Connection of Sensors (CT, Resistive Shunt) ................................................................... 68 3.2 Distinction between 71M6533/71M6534 and 71M6533G/H/71M6534H Parts ..................... 68 3.3 Connecting 5 V Devices ...................................................................................................... 69 3.4 Temperature Measurement ................................................................................................. 69 3.5 Temperature Compensation ............................................................................................... 69 3.5.1 Temperature Coefficients .......................................................................................... 69 3.5.2 Temperature Compensation for VREF ....................................................................... 71 3.5.3 System Temperature Compensation .......................................................................... 72 3.5.4 Temperature Compensation for the RTC ................................................................... 72 3 ...
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... Accuracy over Temperature..................................................................................... 119 5.7 Package Outline Drawings ............................................................................................... 119 5.7.1 71M6533 (100-Pin LQFP) ........................................................................................ 119 5.7.2 71M6534/6534H (120-Pin LQFP) ............................................................................ 120 5.8 Pinout ................................................................................................................................ 121 5.8.1 71M6533/71M6533G/71M6533H Pinout (100-Pin LQFP) ......................................... 121 5.8.2 71M6534/71M6534H Pinout (120-Pin LQFP) ........................................................... 122 5.9 Pin Descriptions ................................................................................................................ 123 5.9.1 Power and Ground Pins........................................................................................... 123 5.9.2 Analog Pins ............................................................................................................. 123 5.9.3 Digital Pins .............................................................................................................. 124 5 ...
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... Figure 50: Typical Wh Accuracy (0. 200 A, 240 V, Room Temperature), Various Load Angles (Differential Mode, CTs) ................................................................................................................ 118 Figure 51: 71M6533/71M6533G/71M6533H 100-Pin LQFP Package Outline ....................................... 119 Figure 52: 71M6534/6534H 120-Pin LQFP Package Outline ................................................................ 120 Figure 53: Pinout for 71M6533/71M6533G/71M6533H LQFP-100 Package ......................................... 121 Figure 54: Pinout for 71M6534/71M6534H LQFP-120 Package ........................................................... 122 Rev 2 5 ...
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... Table 60: CE Transfer Variables .......................................................................................................... 100 Table 61: CE Energy Measurement Variables ...................................................................................... 101 Table 62: Other Transfer Variables ...................................................................................................... 102 Table 63: CE Temperature Registers ................................................................................................... 102 Table 65: CE Parameters for Noise Suppression and Code Version..................................................... 104 Table 66: CE Calibration Parameters ................................................................................................... 104 Table 67: Absolute Maximum Ratings .................................................................................................. 107 6 Rev 2 ...
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Table 68: Recommended External Components .................................................................................. 108 Table 69: Recommended Operating Conditions ................................................................................... 108 Table 70: Input Logic Levels ................................................................................................................ 109 Table 71: Output Logic Levels ............................................................................................................. 109 Table 72: Power-fault Comparator Performance Specifications ............................................................ 109 Table 73: V2 Comparator ...
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VREF IAP IAN VA IBP VBIAS IBN VB VADC MUX ICP ICN VC VREF VBAT TEMP 2.5V_NV MCK PLL RTCLK (32KHz) OSC XIN MPU_DIV (32 kHz) CKOUT_E XOUT RTCA_ADJ RTC 2.5V_NV RST_SUBSEC QREG,PREG RTC_DAY ...
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Hardware Description 1.1 Hardware Overview The Teridian 71M6533 and 71M6534 single-chip energy meter integrate all primary functional blocks required to implement a solid-state electricity meter. Included on the chip are: • An analog front end (AFE) • An Independent ...
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Input Multiplexer The input multiplexer applies the input signals from the pins IAP/IAN, VA, IBP/IBN, VB, ICP/ICN, VC, and IDP/IDN to the input of the ADC. Additionally, using the alternate multiplexer selection, it has the ability to select temperature ...
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Table 1: Signals Selected for the ADC with SLOTn_SEL and SLOTn_ALTSEL (MUX_DIV[3: Regular Slot Time Slot Register 0 SLOT0_SEL[3:0] 1 SLOT1_SEL[3:0] SLOT2_SEL[3:0] 2 SLOT3_SEL[3:0] 3 SLOT4_SEL[3:0] 4 SLOT5_SEL[3:0] 5 SLOT6_SEL[3:0] 6 SLOT7_SEL[3:0] SLOT8_SEL[3:0] SLOT9_SEL[3:0] The duration of each ...
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Address Signal Number (HEX) 0 0x00 1 0x01 2 0x02 3 0x03 4 0x04 1.2.5 Voltage References The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference is trimmed in production to minimize errors caused ...
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CHOP_E[1:0] has four states: positive, reverse, and two toggle states. In the positive state, CHOP_E[1:0] = 01, CROSS and CHOP_CLK are held low. In the reverse state, CHOP_E[1:0] = 10, CROSS and CHOP_CLK are held high. In the first toggle ...
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IAP IAN VA IBP IBN VB ICP ICN VBAT TEMP 1.3 Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE ...
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Table 4: XRAM Locations for ADC Results Address (HEX) 0x07 – 0x09 The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and accumulators. This hardware is controlled through I/O RAM locations EQU[2:0] (equation assist), the ...
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... Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse outputs. Pins DIO8 and DIO9 are used for these pulses. Generally, the XPULSE and YPULSE outputs are updated once on each pass of the CE code, resulting in a pulse frequency maximum of 1260Hz (assuming a MUX frame is 13 CK32 cycles). ...
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The Data RAM is 32 bits wide and uses an external multiplexer appear byte-wide to the MPU. The Data RAM hardware will convert an MPU byte write operation into a read-modify-write operation that requires two Data RAM ...
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PRE_SAMPS[1: and SUM_CYCLES[5:0] = 50, Figure 6 consisting of 2100 samples of 397µs each, followed by the XFER_BUSY interrupt. The sampling in this example is applied signal. ...
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... Typical measurement and metering functions based on the results provided by the internal 32-bit compute engine (CE) are available for the MPU as part of Maxim’s Teridian standard library, which provides demonstration source code to help reduce the design cycle. 1.4.1 Memory Organization and Addressing The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces ...
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If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is disabled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0] ≠ 0 because the 71M6533/71M6534 ADC writes to these locations. ...
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The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers are not affected by the LSB of the DPS register. All DPTR related instructions use the currently selected DPTR for any ...
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Bit Hex/ Addressable Bin X000 X001 D8 WDCON D0 PSW C8 T2CON IRCON C0 IEN1 IP1 IEN0 IP0 A0 P2 DIR2 98 S0CON S0BUF 90 P1 DIR1 88 TCON TMOD 1.4.3 Generic 80515 ...
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Address Reset value Name (Hex) (Hex) IEN0 0xA8 0x00 IP0 0xA9 0x00 S0RELL 0xAA 0xD9 P3 0xB0 0xFF IEN1 0xB8 0x00 IP1 0xB9 0x00 S0RELH 0xBA 0x03 S1RELH 0xBB 0x03 PDATA 0xBF 0x00 IRCON 0xC0 0x00 T2CON 0xC8 0x00 PSW ...
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Stack Pointer (SP, SFR 0x81): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before PUSH and CALL instructions, causing the stack to begin at location 0x08. Data Pointer: The data pointers (DPTR ...
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Stretch CKCON[2:0] 000 001 010 011 100 101 110 111 1.4.4 71M6533/71M6534-Specific Special Function Registers Table 14 shows the location and description of the 71M6533/71M6534-specific SFRs. Table 14: 71M6533/71M6534 Specific SFRs Register SFR (Alternate Name) Address EEDATA 0x9E EECTRL 0x9F ...
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Register SFR (Alternate Name) Address 0xE8[0] 0xE8[1] 0xE8[2] 0xE8[3] IFLAGS 0xE8[4] 0xE8[5] 0xE8[6] 0xE8[7] 0xF8[6:0] INT6 … INT0 INTBITS 0xF8[7] (INT0 … INT6) Only byte operations on the entire INTBITS register should be used when writing. The byte must have ...
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WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps. ...
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Table 17: The S0CON (UART0) Register (SFR 0x98) Bit Symbol Function The SM0 and SM1 bits set the UART0 mode: S0CON[7] SM0 S0CON[6] SM1 S0CON[5] SM20 Enables the inter-processor communication feature. S0CON[4] REN0 If set, enables serial reception. Cleared by ...
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... (T0 and T1 are the timer gating inputs derived from certain DIO pins, see cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock frequency (CKMPU). There are no restrictions on the duty cycle, however to ensure proper recognition of the state, an input should be stable for at least 1 machine cycle ...
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TMOD[5:4] M1:M0 Selects the mode for Timer/Counter 1 as shown in Timer/Counter 0 If TMOD[3] is set, external input signal control is enabled for Counter 0. external gate control. The TR0 bit in the TCON register (SFR 0x88) must ...
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RETI. When an RETI is performed, the processor will return to the instruction that would have been next when the interrupt occurred. When the interrupt condition occurs, the processor will also indicate this ...
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Table 27: TCON Bit Functions (SFR 0x88) Bit Symbol Function TCON[7] TF1 Timer 1 overflow flag. TCON[6] TR1 Not used for interrupt control. TCON[5] TF0 Timer 0 overflow flag. TCON[4] TR0 Not used for interrupt control. TCON[3] IE1 External interrupt ...
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External MPU Interrupts The seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71M6533/71M6534, for example the CE, DIO, RTC, EEPROM interface. The external interrupts are connected as shown ...
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Interrupt Enable Name Location EX_XFER 2002[0] EX_RTC 2002[1] IEN_WD_NROVF 20B0[0] IEN_SPI 20B0[4] EX_FWCOL 2007[4] EX_PLL 2007[5] † The AUTOWAKE and PB flag bits are shown in even though they are not actually related to an interrupt. These bits are set ...
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Table 34: Interrupt Priority Registers (IP0 and IP1) Register Address Bit 7 (MSB) – IP0 SFR 0xA9 – IP1 SFR 0xB9 Interrupt Sources and Vectors Table 36 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag ...
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Data Sheet ...
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... The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery attached to VBAT. Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to Real-Time Clock (RTC) for more information ...
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... The 71M6533 and 71M6534 have two rate adjustment mechanisms. The first is an analog rate adjustment, using RTCA_ADJ[6:0], which trims the crystal load capacitance. Setting RTCA_ADJ[6: minimizes the load capacitance, maximizing the oscillator frequency. Setting RTCA_ADJ[6:0] to 0x7F maximizes the load capacitance, minimizing the oscillator frequency. The adjustable capacitance is approximately: The typical adjustment range is approximately -15 ppm ...
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... Physical Memory Flash Memory The device includes 128 KB (71M6533/H, 71M6534) or 256 KB (71M6533G, 71M6534H) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE and MPU data in RAM as well as of I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations ...
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The flash memory is segmented into individually erasable pages that contain 1024 bytes. Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must begin boundary of the ...
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... KB, addressable at 0x8000 to 0xFFFF. The upper 32 KB space is banked using the I/O RAM FL_BANK[2:0] register as shown in FL_BANK[2: the upper bank is the same as the lower bank. Table 38: Bank Switching with FL_BANK[2:0] 71M6533/H 71M6534H 71M6534 71M6533G FL_BANK[1:0] FL_BANK[2:0] 00 000 01 001 ...
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Optical Interface The device includes an interface to implement an IR/optical port. The pin OPT_TX is designed to directly drive an external LED for transmitting data on an optical link. The pin OPT_RX has the same threshold as the ...
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On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under MPU control. The pin function can be configured by the I/O RAM bits LCD_BITMAPn. Setting LCD_BITMAPn = 1 configures the pin for ...
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Table 41: Data/Direction Registers and Internal Resources for DIO 36-47 DIO – – LCD Segment – – 71M6533 Pin # – – 71M6534 Pin # – – – – Configuration (DIO or LCD segment) LCD_BITMAP[55:48] Data Register – – Direction ...
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Since the control for DIO_24 through DIO_55 is shared with the control for LCD segments, the firmware must take care not to disturb the DIO pins when accessing the LCD segments and vice versa. Usually, this requires reading the I/O ...
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... With a minimum of 15 driver pins always available and a total of 57 (71M6533 (71M6534) driver pins in the maximum configuration, the device is capable of driving between 60 to 228 pixels (71M6533 300 pixels (71M6534 LCD display with 25% duty cycle. At eight pixels per digit, this corresponds to 7 ...
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VBAT in LCD mode). When the LCD_DAC[2:0] bits are set to 000, the DAC is bypassed and powered down. This can be used to reduce current in LCD mode. 1.5.9 Battery Monitor The battery voltage is measured by the ...
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Status Read/ Name Bit Write The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. In this case, a resistor has to be used in series with SDA to avoid data collisions due to limits ...
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EECTRL Byte Written Write -- No HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) Figure 10: 3-wire Interface. Write Command, HiZ=0. EECTRL Byte Written Write -- With HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) Figure ...
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SPI Slave Port The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM locations also able to send commands to the MPU. The interface to the slave ...
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The SPI_FLAG flag bit will be set upon every SPI transaction regardless of whether the command is 11xx xxxx or 10xx xxxx. The SP_ADDR[15:0] bit field is for writing purposes by the host only. Data read from SP_ADDR[15:0] will not ...
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MPU can access the bus. There are no issues with Data RAM access; SPI and the MPU will share the bus with no conflicts for Data RAM access. Table 48: I/O RAM Registers Accessible via SPI Name ...
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SERIAL READ 8 bit CMD PCSZ 0 PSCK (From Host) PSDI PSDO (From 653X) SERIAL WRITE 8 bit CMD PCSZ 0 PSCK (From Host) PSDI (From 653X) PSDO Figure 16: SPI Slave ...
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If enabled with the IEN_WD_NROVF bit in I/O RAM, an interrupt occurs roughly 1 ms before the WDT resets the chip. This can be used to determine the cause of a WDT reset since it allows the code to log ...
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Functional Description 2.1 Theory of Operation The energy delivered by a power source into a load can be expressed as: Assuming phase angles are constant, the following formulae apply: Real Energy [Wh ...
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System Timing Summary Figure 19 summarizes the timing relationships between the input MUX states, the CE_BUSY signal and the two serial output streams. In this example, MUX_DIV[3: and FIR_LEN[1: The duration of each MUX frame ...
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Battery Modes Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode means that the part is operating with system power and that the internal PLL is stable. This mode is the normal ...
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To facilitate transition to SLEEP mode, which is useful when an unprogrammed IC is mounted on a PCB with a battery installed, the Teridian production test programs the following six-byte sequence into the flash location starting at address 0x00000: 0x74 ...
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BROWNOUT Mode In BROWNOUT mode, most non-metering digital functions are active (as shown in ICE, UART, EEPROM, LCD and RTC. In BROWNOUT mode, a low-bias current regulator will provide 2.5 Volts to V2P5 and V2P5NV. The regulator has an ...
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System (V3P3SYS) V1_OK Battery Current BROWNOUT MPU Mode WAKE MPU Clock Source PLL_OK Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns V3P3SYS and VBAT V1_OK Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal RESETZ ...
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VBAT Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal RESETZ VBAT_OK Figure 24: Power-Up Timing with VBAT Only Rev 2 BROWNOUT Xtal 14.5 CK32 cycles 1024 CK32 cycles time 61 ...
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VREF IAP IAN VA VBIAS IBP IBN VB VADC MUX ICP ICN VC VREF VBAT TEMP 2.5V_NV MCK RTCLK (32KHz) OSC XIN MPU_DIV (32 kHz) CKOUT_E XOUT RTCA_ADJ RTC 2.5V_NV RST_SUBSEC QREG,PREG RTC_DAY RTC_DATE ...
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VREF IAP IAN VA VBIAS IBP IBN VB VADC MUX ICP ICN VC VREF VBAT TEMP 2.5V_NV MCK RTCLK (32KHz) OSC XIN MPU_DIV (32 kHz) CKOUT_E XOUT RTCA_ADJ RTC 2.5V_NV RST_SUBSEC QREG,PREG RTC_DAY RTC_DATE ...
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VREF IAP IAN VA IBP VBIAS IBN VB VADC MUX ICP ICN VC VREF IDP IDN VBAT TEMP MCK PLL RTCLK ( 32 KHz ) OSC XIN MPU _ DIV ( 32 kHz ) ...
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Fault and Reset Behavior 2.4.1 Reset Mode When the RESET pin is pulled high, all digital activity stops. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are set to their default states. As long ...
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System Power (V3P3SYS wake- up timer WAKE LCD MPU Mode PLL_OK 2.5.2 Wake on Timer If the part is in SLEEP or LCD mode, it can be awakened by the wake-up timer. Until this timer times out, the ...
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CE/MPU Communication Figure 30 shows the functional relationships between the CE and the MPU. The CE is controlled by the MPU via shared registers in the I/O RAM and in RAM. The CE outputs two interrupt signals to the ...
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... Note: Ferrites or other inductive components must not be connected directly to the sensor input pins (InP, InN Vn). 3.2 Distinction between 71M6533/71M6534 and 71M6533G/H/71M6534H Parts The 71M6533G, 71M6533H, and 71M6534H (high-accuracy) parts go through an additional process of characterization during production which makes them suitable to high-accuracy performance over temperature. ...
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... TRIMT[7:0] I/O RAM register. TC1 and TC2 allow compensation for variations of the reference voltage to within ±40 PPM/°C. For the high-accuracy parts, individualized coefficients TC1 and TC2 can be retrieved from the on-chip fuses via TRIMBGA, TRIMBGB, TRIMM[2:0] (see 71M6533G/H/71M6534H Parts). reference voltage to within ±15 PPM/°C Rev 2 ( ...
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... If the reference voltage is used to measure both voltage and current, the identical errors of ±0.252% add maximum Wh registration error of ±0.504%. The maximum deviation of ±945 PPM (or 0.0945%) for the high-accuracy parts is reached at the temperature extremes. If the reference voltage is used to measure both voltage and current, the identical errors of ± ...
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Error Band (PPM) over Temperature (°C) 2800 2400 2000 1600 1200 800 400 0 -400 -800 -1200 -1600 -2000 -2400 -2800 -40 Figure 34: Error Band for VREF over Temperature (Regular-Accuracy Parts) Error Band (PPM) over Temperature (°C) 1200 800 ...
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System Temperature Compensation In a production electricity meter, the 71M6533 and 71M6534 is not the only component contributing to temperature dependency. A whole range of components (e.g. current transformers, resistor dividers, power sources, filter capacitors) will contribute temperature effects. ...
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Connecting I C EEPROMs EEPROMs or other I C compatible devices should be connected to the DIO pins DIO4 and DIO5, as shown in Figure 37. Pull-up resistors of roughly 10 kΩ to ...
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V3P3D DIO4 Figure 38: Three-Wire EEPROM Connection 4.5 UART0 (TX/RX) The UART0 RX pin should be pulled down kΩ resistor and additionally protected by a 100 pF ceramic capacitor, as shown in Figure 39. 71M6533/71M6534 4.6 ...
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OPT_RX OPT_TX Figure 40: Connection for Optical Components 4.7 Connecting the V1 Pin A voltage divider should be used to establish that safe range when the meter is in MISSION mode (see Figure 41). V1 ...
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VBAT/ V3P3D Reset Switch 0.1µF Figure 42: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) 4.9 Connecting the Emulator Port Pins Even when the emulator is not used, small shunt capacitors to ground ...
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... The oscillator drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to VBAT. ...
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Meter Calibration Once the Teridian 71M6533 and 71M6534 energy meter device has been installed in a meter system, it must be calibrated. A complete calibration includes the following: • Calibration of the metrology section, i.e. calibration for tolerances of ...
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FDS_6533_6534_004 5 Firmware Interface 5.1 I/O RAM and SFR Map –Functional Order In Table 53, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits have no memory storage, writing them has no effect, and reading them ...
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Data Sheet Name Address Bit 7 Digital I/O: 20AF U DIO0 DIO_EEX[1:0] 2008 DIO1 2009 U DIO2 200A U DIO3 200B U DIO4 200C U DIO5 200D U DIO6 200E U R (00) 200F † UMUX_E UMUX_SEL ...
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FDS_6533_6534_004 Name Address Bit 7 RTC0 2015 U RTC1 2016 U RTC2 2017 U RTC3 2018 U RTC4 2019 U RTC5 201A U RTC6 201B RTCADJ_H 201C U RTCADJ_M 201D RTCADJ_L 201E WE 201F LCD Display Interface: LCDX 2020 MUX_SYNC_E ...
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Data Sheet Name Address Bit 7 SPI Interface: SPI… SPE 2070 SP_CMD 2071 SP_ADH 2072 SP_ADL 2073 Pulse Generator: PLS_W 2080 PLS_I 2081 ADC Mux: SLOT0 2090 SLOT1 2091 SLOT2 2092 SLOT3 2093 SLOT4 2094 SLOT5 2096 ...
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FDS_6533_6534_004 5.2 I/O RAM Description – Alphabetical Order The following conventions apply to the descriptions in this table: • Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in flash ...
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Data Sheet CKOUT_E 2004[ COMPSTAT 2003[0] DI_RPB[2:0] 2009[2:0] 0 DIO_R1[2:0] 2009[6:4] 0 DIO_R2[2:0] 200A[2:0] 0 DIO_R3[6:4] 200A[6:4] 0 DIO_R4[2:0] 200B[2:0] 0 DIO_R5[2:0] 200B[6:4] 0 DIO_R6[2:0] 200C[2:0] 0 DIO_R7[2:0] 200C[6:4] 0 DIO_R8[2:0] 200D[2:0] 0 DIO_R9[2:0] 200D[6:4] ...
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FDS_6533_6534_004 DIO_0[7:0] SFR 80 0 DIO_1[7:0] SFR 90 0 DIO_2[7:0] SFR A0 0 DIO_3[6:0] SFR B0 0 DIO_EEX[1:0] 2008[7:6] 0 DIO_PV 2008[2] 0 DIO_PW 2008[3] 0 DIO_PX 200F[3] 0 DIO_PY 200F[2] 0 EEDATA[7:0] SFR 9E 0 EECTRL[7:0] SFR 9F 0 ...
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Data Sheet FIR_LEN[1:0] 2007[3:2] 1 FL_BANK[1:0] SFR B6[1:0] 1 † FL_BANK[2:0] SFR B6[2:0] FLSH_ERASE SFR 94[7:0] 0 [7:0] FLSH_MEEN SFR B2[1] 0 FLSH_PGADR SFR B7 [7:2] 0 [5:0] FLSH_PWE SFR B2[0] 0 FOVRIDE 20FD[ FIR_LEN[1:0] ...
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FDS_6533_6534_004 GP0 20C0 0 … … … GP7 20C7 0 IE_FWCOL0 SFR E8[2] 0 IE_FWCOL1 SFR E8[3] 0 IE_PB SFR E8[4] 0 IE_PLLRISE SFR E8[6] 0 IE_PLLFALL SFR E8[7] 0 IEN_SPI 20B0[4] IEN_WD_NROVF 20B0[0] 0 IE_XFER SFR E8[0] 0 IE_RTC ...
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Data Sheet LCD_BITMAP [63:61], 2027[7:5,3:0] 0 † [59:56] LCD_BITMAP 2028[7:0] 0 [71:64] LCD_BLKMAP18 205A[3:0] 0 [3:0] LCD_CLK[1:0] 2021[1:0] 0 LCD_DAC[2:0] 20AB[3:1] 0 LCD_E 2021[5] 0 LCD_MODE[2:0] 2021[4: Configuration for DIO43/SEG63 through DIO41/SEG61 and DIO39/SEG59 through ...
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FDS_6533_6534_004 LCD_ONLY 20A9[5] 0 LCD_SEG0[3:0] 2030[3:0] 0 … … … LCD_SEG18[3:0] 2042[3:0] 0 LCD_SEG19[3:0] 2043[3:0] 0 … … … LCD_SEG31[3:0] 204F[3:0] 0 † LCD_SEG32[3:0] 2050[3:0] 0 LCD_SEG33[3:0] 2051[3:0] 0 … … … LCD_SEG41[3:0] 2059[3:0] 0 † LCD_SEG42[3:0] 2030[7:4] 0 LCD_SEG43[3:0] ...
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Data Sheet LCD_Y 2021[6] 0 M26MHZ 2005[4] 0 M40MHZ 2005[0] 0 MPU_DIV[2:0] 2004[2:0] 0 MUX_ALT 2005[2] 0 MUX_DIV[3:0] 209D[3:0] 0 MUX_SYNC_E 2020[7] 0 OPT_FDC[1:0] 2007[1: LCD Blink Frequency (ignored if blink is disabled or if ...
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... The modulation is applied after any inversion caused by OPT_TXINV Indicates that system power is present and the clock generation PLL is settled. Determines the maximum width of the pulse (low going pulse). The maximum pulse width is (2*PLS_MAXWIDTH + 1)*T FF R/W If PLS_INTERVAL = the sample time (397 µ ...
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Data Sheet QREG[1:0] 201E[1:0] 0 RST_SUBSEC 2010[0] 0 RTCA_ADJ[6:0] 2011[6:0] 40 RTC_SEC[5:0 2015 * RTC_MIN[5:0] 2016 * RTC_HR[4:0] 2017 * RTC_DAY[2:0] 2018 * RTC_DATE[4:0] 2019 * RTC_MO[3:0] 201A * RTC_YR[7:0] 201B * RTM_E 2002[3] 0 RTM0[7:0] 2060[9:8] ...
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FDS_6533_6534_004 SLOT0_ALTSEL 10 2096[3:0] [3:0] SLOT1_ALTSEL 1 2096[7:4] [3:0] SLOT2_ALTSEL 2097[3:0] 11 [3:0] … … … SLOT8_ALTSEL 8 209A[3:0] [3:0] SLOT9_ALTSEL 9 209A[7:4] [3:0] SP_ADDR[15:8] 2072[7:0] – SP_ADDR[7:0] 2073[7:0] SP_CMD 2071 – SPE 2070[7] 0 SPI_FLAG 20B1[4] SUBSEC[7:0] – 2014[7:0] ...
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... WAKE_PRD and WAKE_RES. The autowake timer is reset and disarmed whenever – W the processor is in MISSION mode or BROWNOUT mode. The timer must be armed at least three RTC cycles before the SLEEP or LCD-ONLY mode is commanded. Sleep time. Time = WAKE_PRD[2:0]*WAKE_RES. The default = 001. The maximum – R/W value is 7. – ...
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CE Interface Description 5.3.1 CE Program The CE performs the precision computations necessary to accurately measure power. These computations include offset cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag detection and voltage phase measurement. All ...
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Environment Before starting the CE using the CE_E bit, the MPU has to establish the proper environment for the CE by implementing the following steps: • Load the CE data into RAM. • Establish the equation to be applied ...
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CE Calculations Table 55: CE EQU[2:0] Equations and Element Input Mapping Watt & VAR Element Input Mapping Formula EQU[ 2:0] (WSUM/VARS W0SUM/ VAR0SUM UM element, 2W 1φ) VA*(IA-IB)/ element, 3W 1φ) VA*IA + ...
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CE Status and Control CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. It contains sag warning flags for phase ...
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... When 0, enables the control of GAIN_ADJ by the CE. The number of consecutive voltage samples below SAG_THR 80 before a sag alarm is declared. The maximum value is 255. (0x50) SAG_THR is at address 0x24. The combination of FREQSEL1 and FEQSEL0 selects the phase to be used for the frequency monitor, the phase-to-phase lag ...
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PULSE_FAST [1] PULSE_SLOW [0] Table 59: Sag Threshold and Gain Adjust Control CE Name Address SAG_THR 0x24 2.39*10 GAIN_ADJ 0x40 5.3.8 CE Transfer Variables When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the ...
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WSUM_X and VARSUM_X are the signed sum of Phase-A, Phase-B and Phase VARh values according to the metering equation specified in the I/O RAM register EQU[2:0]. WxSUM_X is the Wh value accumulated for phase x in the last ...
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CE Name Address FREQ_X 0x82 0x97 PH_AtoB_X PH_AtoC_X 0x98 MAINEDGE_X 0x83 VBAT_SUM_X 0x84 5.3.9 Temperature Measurement and Temperature Compensation Table 63 describes the CE registers supporting temperature measurement and temperature compensation. CE Name Default Address TEMP_RAW 0x81 TEMP_X 0x9D 0x39 ...
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... PULSE_WIDTH allows adjustment of the pulse width for compatibility with calibration and other external equipment. The minimum pulse width possible is 66.16µs. The maximum time jitter is1/6 of the MUX cycle period (nominally 67 µs) and is independent of the number of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is 67 ppm. ...
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Noise Suppression and Version Parameters Table 65 shows the CE parameters used for suppression of noise due to scaling and truncation effects. Table 65: CE Parameters for Noise Suppression and Code Version CE Name Default Address QUANTA 0x26 QUANTB ...
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CE Flow Diagrams Figure 45 through Figure 47 show the data flow through the CE in simplified form. Functions not shown include delay compensation, sample interpolation, scaling and the processing of meter equations. multiplexer ...
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VARA VARB VARC PRE_SAMPS SQUARE Figure 47: CE Data Flow: Squaring and Summation Stages 106 SUM WASUM_X WBSUM_X Σ WCSUM_X VARASUM_X VARBSUM_X VARCSUM_X Σ SUM_CYCLES=60 & ...
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... Absolute Maximum Ratings Table 67 shows the absolute maximum ranges for the device. Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions not implied ...
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Recommended External Components Table 68: Recommended External Components Name From To C1 V3P3A AGND C2 V3P3D GNDD CSYS V3P3SYS GNDD C2P5 V2P5 GNDD XTAL XIN XOUT CXS XIN AGND CXL XOUT AGND Notes: 1. AGND and GNDD should be ...
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Performance Specifications 6.4.1 Input Logic Levels Parameter † Digital high-level input voltage † Digital low-level input voltage , V Input pull-up current E_RXTX, E_ISYNC E_RST, CKTEST Other digital inputs Input pull down current ICE_E RESET ...
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... CKMPU = 614 kHz No Flash Memory write V3P3A current RTM_E=0, ECK_DIS=1, VBAT current ADC_E=1, ICE_E=0 Normal Operation as above, V3P3SYS current, except write Flash at maximum Write Flash rate, CE_E = 0, ADC_ VBAT=3.6V VBAT current 6.4.7 V3P3D Switch Table 76: V3P3D Switch Performance Specifications Parameter On resistance – V3P3SYS to V3P3D On resistance – ...
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... Parameter V2P5 V2P5 load regulation VBAT voltage requirement PSRR ΔV2P5/ΔVBAT 6.4.10 Crystal Oscillator Table 79: Crystal Oscillator Performance Specifications Parameter Maximum Output Power to Crystal 2 XIN to XOUT Capacitance 2 Capacitance to GNDD XIN XOUT 1 This specification defines a nominal relationship rather than a measured parameter. Correct circuit operation will be verified with other specs that use this nominal relationship as a reference ...
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... VLC0 Voltage , ⅓ bias VLC1 Impedance VLC0 Impedance † VLCD is V3P3SYS in MISSION mode and VBAT in BROWNOUT and LCD modes. †† Specified as percentage of VLC2, the maximum LCD voltage. 112 Condition 1 ≤ LCD_DAC ≤ 7 DAC ) − 019 V Condition † ...
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Temperature Sensor Table 83 shows the performance for the temperature sensor. The LSB values do not include the 8-bit left shift at CE input. Table 83: Temperature Sensor Performance Specifications Parameter Nominal relationship: N( [M40MHZ, M26MH] ...
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... Table 84: VREF Performance Specifications Parameter VREF output voltage, VREF(22) VREF chop step VREF power supply sensitivity ΔVREF / ΔV3P3A VREF input impedance VREF output impedance 3 VNOM definition If TRIMBGA and TRIMBGB are available (71M6533G/H, 71M6534H) 4 Definitions VNOM temperature coefficients TC1 TC2 VREF(T) deviation from VNOM(T) 6 VREF ...
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ADC Converter, V3P3A Referenced Table 85 shows the performance specifications for the ADC converter, V3P3A referenced. For this data, FIR_LEN=2, [M40MHZ, M26MHZ]=[00], unless stated otherwise, VREF_DIS=0. LSB values do not include the 8-bit left shift at the CE input. ...
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Timing Specifications 6.5.1 Flash Memory Table 86: Flash Memory Timing Specifications Parameter Flash Read Pulse Width Flash write cycles Flash data retention Flash data retention Flash byte writes between page or mass erase operations Write Time per Byte Page ...
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SPI Slave Port (MISSION Mode) Table 90: SPI Slave Port (MISSION Mode) Timing Parameter t PCLK cycle time SPIcyc t Enable lead time SPILead t Enable lag time SPILag t PCLK pulse width: SPIW High Low t PCSZ to ...
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Typical Performance Data 6.6.1 Accuracy over Current Figure 49 shows meter accuracy over current for various line frequencies. over current at various load angles. 6533/34 Wh Performance, Equation 5, 45 Hz 240 V - ...
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... PPM/°C for the 71M6533/71M6534 and within ±15 PPM/°C for the 71M6533H/71M6534H. 6.7 Package Outline Drawings 6.7.1 71M6533 (100-Pin LQFP) Controlling dimensions are in mm. 1 14.000 +/- 0.200 0.225 +/- 0.045 Figure 51: 71M6533/71M6533G/71M6533H 100-Pin LQFP Package Outline Rev 2 15.7(0.618) 16.3(0.641) Top View MAX. 1.600 1.50 +/- 0.10 0.50 TYP. ...
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LQFP) Controlling dimensions are in mm. 7.000 120 1 13.950 +/- 0.100 0.180 +/- 0.050 Figure 52: 71M6534/6534H 120-Pin LQFP Package Outline 120 16.000 +/- 0.200 14.000 +/- 0.100 8.000 MAX. 1.600 1.400 +/- 0.050 0.400 0.100 ...
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... SEG4/PSDO 10 SEG5/PCSZ 11 SEG37/DIO17 12 SEG38/DIO18/MTX 13 DIO56 14 DIO57 15 DIO58 16 DIO3 17 COM0 18 COM1 19 COM2 20 COM3 21 SEG67/DIO47 22 SEG68/DIO48 23 SEG69/DIO49 24 SEG70/DIO50 25 Figure 53: Pinout for 71M6533/71M6533G/71M6533H LQFP-100 Package Rev 2 TERIDIAN 71M6533 71M6533G 71M6533H GNDD 75 RESET 74 V2P5 73 VBAT SEG31/DIO11 70 SEG30/DIO10 69 SEG29/DIO9/YPULSE 68 SEG28/DIO8/XPULSE 67 SEG41/DIO21 66 SEG40/DIO20 65 SEG39/DIO19 64 SEG27/DIO7/RPULSE 63 SEG26/DIO6/WPULSE ...
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Pinout (120-Pin LQFP) GNDD 1 SEG9/E_RXTX 2 DIO2/OPT_TX 3 TMUXOUT 4 SEG66/DIO46 SEG3/PCLK 7 V3P3D 8 SEG19/CKTEST 9 V3P3SYS 10 SEG4/PSDO 11 SEG5/PCSZ 12 SEG54/E_TBUS3 13 SEG53/E_TBUS2 14 SEG52/E_TBUS1 15 SEG51/E_TBUS0 16 SEG37/DIO17 17 SEG38/DIO18/MTX ...
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Pin Descriptions Pins marked with an asterisk (e.g. V2*) are only available on the 71M6534. 6.9.1 Power and Ground Pins Name Type Circuit Description – GNDA P Analog ground: This pin should be connected directly to the ground plane. ...
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Digital Pins Name Type Circuit Description COM3,COM2 COM1,COM0 SEG0…SEG2, SEG8 SEG12…SEG18, SEG20…SEG23 SEG24/DIO4 … SEG31/DIO11, SEG32/DIO12* SEG33/DIO13 … SEG41/DIO21, SEG42/DIO22* SEG43/DIO23 … SEG47/DIO27, SEG48/DIO28* SEG49/DIO29, SEG50/DIO30, SEG56/DIO36* I … SEG59/DIO39* SEG61/DIO41, SEG62/DIO42* ...
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E_RXTX/SEG9 I E_RST/SEG11 I E_TCLK/SEG10 ICE_E I 2 CKTEST/SEG19 MUXSYNC/SEG7 TMUXOUT O 4 OPT_RX/DIO1 I OPT_TX/DIO2 I RESET ...
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I/O Equivalent Circuits V3P3D V3P3D 110K Digital CMOS Input Input Pin GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D Digital CMOS Input Input Pin 110K GNDD GNDD ...
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... Bulk ±15 256 ±40 128 Tape and reel ±15 256 ORDERING PACKAGE NUMBER MARKING 71M6533-IGT/F 71M6533-IGT 71M6533H-IGT/F 71M6533H-IGT 71M6533G-IGT/F 71M6533G-IGT 71M6533-IGTR/F 71M6533-IGT 71M6533H-IGTR/F 71M6533H-IGT 71M6533G-IGTR/F 71M6533G-IGT 71M6534-IGT/F 71M6534-IGT 71M6534H-IGT/F 71M6534H-IGT 71M6534-IGTR/F 71M6534-IGT 71M6534H-IGTR/F 71M6534H-IGT 3.5.1 for details. 127 ...
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Appendix A: Acronyms AFE Analog Front End AMR Automatic Meter Reading ANSI American National Standards Institute CE Compute Engine DIO Digital I /O DSP Digital Signal Processor FIR Finite Impulse Response Inter-IC Bus ICE In-Circuit Emulator IEC ...
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Appendix B: Revision History REVISION REVISION NUMBER DATE 2 2/12 1.2 August 3, 2010 Rev 2 DESCRIPTION 1) Added Guaranteed By Design notes to the Electrical Specifications. 2) Added explanation on NV properties of RTCA_ADJ[ ] and PREG/QREG[ ] and ...
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... Added VBAT_SUM_X to 21) Section 5.3.12: Added CAL_ID location. 22) Section 1.1.1: Updated flow diagrams. 23) Added 71M6533G (256 KB). 24) Updated value for capacitor at XOUT (7 pF). 25) Added description of delay compensation in CE (1.3.6). 26) Added description of error bands for VREF in 3.5.1. 27) Replaced Accuracy with Trim Deviation in Ordering Information. ...
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... March 6, 2009 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time ...
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Rev 2 ...