DS8007A Maxim, DS8007A Datasheet - Page 22

• Manufacturer Part Number: DS8007A
• Description: The DS8007A multiprotocol dual smart card interface is an automotive grade, low-cost, dual smart card reader interface supporting all ISO 7816, EMV™, and GSM11-11 requirements
• Manufacturer: Maxim

Multiprotocol Dual Smart Card Interface
R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to u1u1uuu0b on RIU = 0.
Bit 7: Clock Switch (CLKSW). This status bit indicates
the clock (f
selected card interface and thus may be used to deter-
mine when a requested clock switch has occurred
properly. When CLKSW is set 1, the clock has switched
from f
the clock has switched from f
Bit 6: FIFO Empty Status Bit (FE). This bit is set to 1
when the receive FIFO is empty. This bit is cleared to 0
when at least one character remains in the receive FIFO.
Bit 5: Block Guard Time Status Bit (BGT). This status
bit is linked to an ETU counter for the currently selected
card interface, and is intended for use in verifying that
the block guard time is always being met. The counter
restarts on every start bit and stops only if the terminal
count is reached. The terminal count is dependent
upon the selected protocol (16 ETU for T = 0 and 22
ETU for T = 1). This bit is cleared to 0 on every start bit.
Bit 4: Control Ready (CRED). This bit signals the host
device that the DS8007A is ready to handle the next
write operation to UTR or TOC or the next read opera-
tion of URR. When CRED = 0, the DS8007A is still work-
ing on the previous operation and cannot correctly
process the new read/write request. When CRED = 1,
the DS8007A is ready for the next read/write request.
This “busy” bit allows the DS8007A to meet the timing
constraints of high-speed host devices. The CRED bit
remains low:
22
Address 0Ch
• 3 clock cycles after the rising edge of RD before
• 3 clock cycles after the rising edge of WR (or CS)
reading URR.
before writing to UTR.
______________________________________________________________________________________
XTAL
/ n to f
XTAL
CLKSW
/ n or f
R-0
INT
7
/ 2; when CLKSW is cleared to 0,
INT
/ 2) being sourced by the
INT
R-1
FE
6
/ 2 to f
XTAL
BGT
R-0
/ n.
5
CRED
R-1
4
The CRED bit timing applies to asynchronous mode
only; this bit is forced to 1 in synchronous mode.
Bit 3: Presence Card B (PRB). This bit is set to 1 when
card B presence is detected and is cleared to 0 when
card B is not present.
Bit 2: Presence Card A (PRA). This bit is set to 1 when
card A presence is detected and is cleared to 0 when
card A is not present.
Bit 1: INTAUX Bit (INTAUX). This bit reflects the state
of the INTAUX pin. This bit is set when the INTAUX pin
is high and is cleared when the INTAUX pin is low.
Bit 0: Transmit Buffer Empty/Receive Buffer Full
(TBE/RBF). This bit signals special conditions relating
to the ISO UART and associated hardware. This bit is
not set when the last character is transmitted by the
UART when LCT = 1.
This bit is set to 1 when:
This bit is cleared to 0 when:
• 1/PSC (min) ETU and 2/PSC (max) ETU after the
• UCR1.T/R is changed from 0 (receive mode) to 1
• A character is transmitted by the UART.
• The receive FIFO becomes full.
• The ISO UART is reset by RIU = 0.
• A character is written to the UART transmit register
• A character is read from the receive FIFO in
• UCR1.T/R is changed from 1 (transmit mode) to 0
rising edge of WR (or CS) before writing to TOC
(transmit mode).
(UTR) in transmit mode.
receive mode.
(receive mode).
PRB
Mixed Status Register (MSR)
R-0
3
PRA
R-0
2
INTAUX
R-0
1
TBE/RBF
R-0
0