ADV7162KS220 Analog Devices Inc, ADV7162KS220 Datasheet - Page 16

• Manufacturer Part Number: ADV7162KS220
• Description: IC DAC VIDEO COLOR 96BIT 160MQFP
• Manufacturer: Analog Devices Inc
• Type: Video DACr

Specifications of ADV7162KS220

• Rohs Status: RoHS non-compliant
• Applications: HDTV
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP

ADV7160/ADV7162
Other pixel data signals latched into the device by LOADIN
include SYNC, BLANK, TRISYNC and PS0
Internally, data is pipelined through the part by the differential
pixel clock inputs, CLOCK and CLOCK or by the internal
pixel clock generated by the PLL on-board. The LOADIN
control signal need only have a frequency synchronous relation-
ship to the pixel CLOCK (see “Pipeline Delay & On-Board
Calibration” section). A completely phase independent
LOADIN signal can be used with the ADV7160/ADV7162,
allowing the CLOCK to occur anywhere during the LOADIN
cycle.
Alternatively, the LOADOUT signal of the ADV7160/ADV7162
can be used. LOADOUT can be connected either directly or
indirectly to LOADIN. Its frequency is automatically set to the
correct LOADIN requirement.
SYNC, BLANK
The BLANK and SYNC video control signals drive the analog
outputs to the Blank and Sync levels respectively. These signals
are latched into the part on the rising edge of LOADIN. The
SYNC information is encoded onto the IOG analog signal
when Bit CR22 of Command Register 2 is set to “1,” the IOR
analog signal when Bit CR41 of Command Register 4 is set to
“1” and the IOB analog signal when Bit CR42 of Command
Register 4 is set to “1.” The SYNC input is ignored if CR22,
CR41 and CR42 are set to logic “0.”
SYNCOUT
In some applications where it is not permissible to encode
SYNC on green (IOG), blue (IOB), or red (IOR), SYNCOUT
can be used as a separate TTL digital SYNC output. This has
the advantage over an independent (of the ADV7160/ADV7162)
SYNC in that it does not necessitate knowing the absolute pipe-
line delay of the part. This allows complete independence
between LOADIN/Pixel Data and CLOCK. The SYNC input
is connected to the device as normal with Bit CR22 of Com-
mand Register 2, Bit CR41 of Command Register 4 and Bit
CR42 of Command Register 4 are set to “0” thereby preventing
SYNC from being encoded onto IOG, IOR and IOB. The out-
put signal generates a TTL SYNCOUT with correct pipeline
delay which is capable of directly driving the composite SYNC
signal of a computer monitor.
TRISYNC
This input is used to generate a HDTV Sync on any of the DAC
outputs. Bit CR17 of Command Register 1 is set to “1”, en-
abling TRISYNC. When TRISYNC is low, the analog output
which has Sync enabled goes to the tri-sync level.
PS0
These multifunctional TTL compatible inputs can be config-
ured for three separate functions. The eight PS inputs are mul-
tiplexed to provide two bits which are used to provide one of
three different functions. The function is selected by Bit CR14
and Bit CR15 of Command Register 1.
CR15
0
0
1
1
A-D
–PS1
CR14
0
1
0
1
A-D
(Palette Priority Select Inputs)
Color Mode
Palette Select Mode
Bypass Mode Control (ADV7160 Only)
Overlay Color Mode
Ignore PS Inputs
A-D
– PS1
A-D
.
–16–
However, in 8:1 Mode, for 8-Bit Pseudo Color, the unused Blue
Pixel Inputs are used to provide 8 extra PS inputs. The bypass
mode is unavailable in this case.
Palette Select Mode
These pixel port select inputs effectively determine whether the
devices RGB analog outputs are turned-on or shut down. When
the analog outputs are shut down, IOR, IOG and IOB are
forced to 0 mA regardless of the state of the pixel and control
data inputs. This state is determined on a pixel by pixel basis as
the PS0–PS1 inputs are multiplexed in exactly the same format
as the pixel port color data. These controls allow for switching
between multiple palette devices. If the values of PS0 and PS1
match the values programmed into bits MR16 and MR17 of the
Mode Register, then the device is selected, if there is no match
the device is effectively shut down.
Bypass Mode Control (ADV7160 Only)
In this mode PS1 is used to switch between one of the color
modes through the Color Palette and one of the Palette Bypass
modes on a pixel by pixel basis. The color mode through the
palette is selected using Bits CR27–CR24 of Command Regis-
ter 2. The Bypass Color Mode is selected using Bits CR17 and
CR16 of Command Register 1. PS1 then switches between the
Palette Color Mode, and the Bypass Color Mode. The PS0 in-
put continues to act as an overlay input, allowing Overlay Color
1 to be displayed.
This mode is not available if using the ADV7162.
Overlay Color Mode
In this mode, the PS inputs provide control for a three color
overlay. Whenever the value other than “00” is placed on the
overlay inputs, the corresponding overlay color is displayed.
When the overlay inputs contain “00” the color is specified by
the main pixel inputs.
CLOCK CONTROL CIRCUIT
The ADV7160/ADV7162 has an integrated Clock Control Cir-
cuit (Figure 16). This circuit is capable of both generating the
ADV7160/ADV7162’s internal clocking signals as well as exter-
nal graphics subsystem clocking signals. Total system synchro-
nization can be attained by using the parts output clocking
signals to drive the controlling graphics processor’s master clock
as well as the video frame buffers shift clock signals.
CLOCK, CLOCK Inputs
The Clock Control Circuit is driven by the pixel clock inputs,
CLOCK and CLOCK. These inputs can be driven by a differ-
ential ECL oscillator running from a +5 V supply.
PS0
0
0
1
PS1
0
1
x
Color Mode
Palette Color Mode (CR27–CR24)
Bypass Color Mode (CR17–CR16)
Overlay Color 1
REV. 0