ADV7162KS220 Analog Devices Inc, ADV7162KS220 Datasheet - Page 27

• Manufacturer Part Number: ADV7162KS220
• Description: IC DAC VIDEO COLOR 96BIT 160MQFP
• Manufacturer: Analog Devices Inc
• Type: Video DACr

Specifications of ADV7162KS220

• Rohs Status: RoHS non-compliant
• Applications: HDTV
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP

REV. 0
then performing an MPU access to the Control Register. When
accessing Control Registers in the range 200H to 204H, and
when accessing the cursor image, the Address Register auto-
increments after each register access. On accessing the last cur-
sor image location at address 7FFH, the address register reverts
to address 000H. The Address Register also auto-increments
after a blue access, when accessing color registers in the address
range 303H to 304H.
ID Register
(Address Reg (A10–A0) = 003H)
This is an 8-bit wide “Identification” read-only register. For the
ADV7160 it will always return the hexadecimal value 76H. For
the ADV7162 it will always return the hexadecimal value 79H.
Pixel Mask Register
(Address Reg (A10–A0) = 004H)
The contents of the pixel mask register are individually bit-wise
logically ANDed with the Red, Green and Blue pixel input
stream of data. It is an 8-bit read/write register with D0 corre-
sponding to R0, G0 and B0. For normal operation, this register
is set with FFH.
COMMAND REGISTER 1 (CR1)
(Address Reg (A10–A0) = 005H)
This register contains a number of control bits as shown in the
diagram. CR1 is a 10-bit wide register. However for program-
ming purposes, it may be considered as an 8-bit wide register
(CR19 to CR18 reserved).
Figure 40 shows the various operations under the control of
CR1. This register can be read from as well written to. In write
mode zero should be written to CR12. In read mode, CR19
and CR18 are returned as zeros.
COMMAND REGISTER 1-BIT DESCRIPTION
Calibration Control (CR10)
This bit automatically calibrates the on-board LOADIN/
LOADOUT synchronization circuit on every vertical Sync.
MR15 of Mode Register MR1 must be set to “0.”
*
THESE BITS ARE READ-ONLY
RESERVED BITS.
A READ CYCLE WILL RETURN
ZEROS "00."
CR19
RESERVED*
CR17 CR16
0
0
1
1
BYPASS COLOR MODE
CR18
0
1
0
1
15-BIT BYPASS
16-BIT BYPASS
24-BIT BYPASS
RESERVED
CR17
Figure 40. Command Register 1 (CR1) (CR19–CR10)
**THIS MODE IS ONLY AVAILABLE
CR15 CR14
ON THE ADV7160.
IT IS RESERVED ON THE ADV7162.
CR16
0
0
1
1
PS FUNCTION CONTROL
CR13
0
1
0
1
1
0
PALETTE SELECTS
BYPASS MODE**
OVERLAYS
IGNORE PS INPUTS
ADDRESS REGISTER
CR15
HI-BYTE CONTROL
NO ACCESS TO HI-BYTE
(ADV7150 COMPATIBLE)
ACCESS TO HI-BYTE
CR14
–27–
Hi-Byte Control (CR13)
This bit enables access to the Hi Byte of the Address Register.
When CR13 is set to Logic “0”, the part is compatible to the
ADV7150. To access the hi-byte of the address register, this bit
is set to Logic “1.”
PS Function Control (CR15–CR14)
These bits control the functions of the PS inputs. They are
used to enable the Overlay Mode, Bypass Mode or the Palette
Select Mode. In Palette Select Mode (CR15 and CR14 = “0”),
these inputs are used to multiplex the RGB outputs of a number
of devices. On a pixel by pixel basis, PS1 and PS0 are com-
pared against the PS match bits, MR17 and MR16. If they
match, then the part behaves normally. If they don’t match,
then the analog output currents are switched to zero for that
clock cycle, thus allowing another device, whose PS match bits
match during this time, to drive the monitor. In Bypass Mode
(CR15 = “0,” CR14 = “1”), PS1 is used to switch between one
of the color modes through the Color Palette and one of the Pal-
ette Bypass Modes, on a pixel by pixel basis. The color mode
through the palette is selected using CR17 and CR16. It is il-
legal to program CR27 to CR24 to select one of the bypass modes
when using the PS bits to select a bypass mode at the pixel rate.
This switching on a pixel by pixel basis is only allowed when using
an ADV7160 device. Therefore, for the ADV7162, this mode
(CR15 = “0,” CR14 = “1”), is reserved and should not be used.
In Overlay Mode (CR15 = “1,” CR14 = “0”), the PS inputs
provide control for a three color overlay. Whenever a value
other than “00” is placed on the overlay inputs, the correspond-
ing overlay color is displayed. When the overlay inputs contain
“00,” the color is specified by the pixel inputs.
When CR15 and CR14 = “1,” the PS inputs are completely
ignored. There is no overlay, no bypass switching and the RGB
outputs are enabled.
Bypass Color Mode Control (CR17–CR16)
These bits control the mode during bypass switching. There are
three different modes: 24-bit Bypass, 16-bit Bypass or 15-bit
Bypass Mode.
CR13
THIS BIT SHOULD
BE SET TO ZERO
TEST MODE CONTROL
CR11
0
1
CR12
CR12
(0)
DISABLE
ENABLE TEST
MODE
CR11
ADV7160/ADV7162
CR10
CR10
1
0
CALIBRATION
CONTROL
CALIBRATES ON
EVERY VERTICAL
SYNC (MR15=0)
DISABLE