MAX9268 Maxim, MAX9268 Datasheet
MAX9268
Available stocks
Related parts for MAX9268
MAX9268 Summary of contents
Page 1
... UART link between the serializer and deserializer. An electronic control unit (ECU), or microcontroller (FC), can be located on the serializer side of the link (typical for video display), on the MAX9268 side of the link (typical for image sensing both sides. In addition, the control channel enables ECU/FC control of ...
Page 2
... For detailed information on package thermal considerations, refer to Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
Page 3
Gigabit Multimedia Serial Link Deserializer DC ELECTRICAL CHARACTERISTICS (continued 3.0V to 3.6V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL AND UART I/O, OPEN-DRAIN ...
Page 4
Gigabit Multimedia Serial Link Deserializer with LVDS System Interface DC ELECTRICAL CHARACTERISTICS (continued 3.0V to 3.6V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL Output Short-Circuit Current ...
Page 5
Gigabit Multimedia Serial Link Deserializer AC ELECTRICAL CHARACTERISTICS (continued 3.0V to 3.6V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL LVDS Output Pulse Position t LVDS Output ...
Page 6
... EQUALIZATION 40 NO PE, 5.2dB EQUALIZATION 20 -12 BER CAN BE AS LOW AS 10 FOR CABLE LENGTHS LESS THAN 10m STP CABLE LENGTH (m) OUTPUT POWER SPECTRUM vs. TXCLKOUT_ FREQUENCY (VARIOUS MAX9268 SPREAD) -10 f TXCLKOUT_ -20 0% SPREAD -30 -40 -50 -60 -70 -80 2% SPREAD -90 4% SPREAD -100 80 30.5 31 ...
Page 7
... Bus-Width Select. Output width selection requires external pulldown or pullup resistor. Set BWS 1 BWS = low for 3-channel mode. Set BWS = high for 4-channel mode. Interrupt Input. Requires external pulldown or pullup resistor. A transition on the MAX9268’s 2 INT INT input toggles the GMSL serializer’s INT output. ...
Page 8
... GND Digital and I/O Ground Receive/Serial Data. UART receive RX/SDA pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9268’s UART mode, RX/SDA is the SDA input/output of the MAX9268’s I Transmit/Serial Clock. UART transmit TX/SCL to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9268’s UART SCL is the SCL output of the MAX9268’ ...
Page 9
... LVDS System Interface Pin Description (continued) FUNCTION CLK SSPLL DIV RGB[17:0] RGB VIDEO DE DE 8b/10b DECODE/ UNSCRAMBLE RES/CNTL1 CNTL1/RES FIFO (4-CH) CNTL2 ACB AUDIO FCC UART/I SCK WS TX/SCL Functional Diagram CDR Rx/EQ PLL SERIAL TO PARALLEL Tx REVERSE CONTROL CHANNEL MAX9268 2 C RX/SDA IN+ IN- 9 ...
Page 10
... Gigabit Multimedia Serial Link Deserializer with LVDS System Interface IN+ V CMR IN- V ROH 0 ROH 0 ROH (IN+) - (IN Figure 1. Reverse Control-Channel Output Parameters V IN+ Figure 2. Test Circuit for Differential Input Measurement 10 _____________________________________________________________________________________ MAX9268 REVERSE CONTROL-CHANNEL TRANSMITTER 0 0 ID( IN- ...
Page 11
Gigabit Multimedia Serial Link Deserializer TXOUT_- TXCLKOUT- V OS(-) TXOUT_+ TXCLKOUT+ V OD(-) (TXOUT_+) - (TXOUT_-) (TXCLKOUT+) - (TXCLKOUT-) Figure 3. LVDS Output Parameters TXOUT0+ TO TXOUT3+ TXOUT0- TO TXOUT3- Figure 4. Worst-Case Pattern Output t R TX/ SCL RX/ ...
Page 12
... Gigabit Multimedia Serial Link Deserializer with LVDS System Interface C L MAX9268 SINGLE-ENDED OUTPUT LOAD 0 I0VDD 0 I0VDD t R Figure 6. Single-Ended Output Rise-and-Fall Times FIRST BIT N N+1 N+2... IN+/IN- TXOUT_+/ TXOUT_- TXCLKOUT+/- t SD Figure 8. Deserializer Delay IN+/- V PWDN IH1 t PU LOCK Figure 10. Power-Up Delay ...
Page 13
... LVDS System Interface serializer side of the link (typical for video display), on the MAX9268 side of the link (typical for image sensing both sides. In addition, the control channel enables ECU/FC control of peripherals in the remote side, such as backlight control, grayscale Gamma correction, camera module, and touch screen ...
Page 14
Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Table 1. Power-Up Default Register Map (see Table 12) (continued) REGISTER POWER-UP ADDRESS DEFAULT (hex) (hex) 0x04 0x03 or 0x13 0x05 0x24 or 0x29 0x06 0x0F 0x07 0x54 0x08 0x30 0x09 ...
Page 15
... ADD1 affect the default device address values stored in the MAX9268 only. The default device address values stored in the GMSL serializer may differ (see the 3-Level Inputs for Default Device Address section). ** for the serializer address for the deserializer address. ...
Page 16
... The LVDS output has two selectable widths: 3-channel and 4-channel. The MAX9268 outputs 3- or 4-channel LVDS (Table 3). Serial data is mapped to outputs on the MAX9268 according to Figures 12 and 13. In 3-chan- nel mode, TXOUT3_ and CNTL1, CNTL2/MCLK are not available. For both modes, the SD/CNTL0, SCK, and WS ...
Page 17
Gigabit Multimedia Serial Link Deserializer TXCLKOUT- TXCLKOUT+ TXOUT0+ /TXOUT0- TXOUT1+/TXOUT1- TXOUT2+/TXOUT2- TXOUT3+/TXOUT3- CNTL1 CNTL2/MCLK SD/CNTL0 *ONLY WHEN I Figure 12. LVDS Output Timing TXCLKOUT- TXCLKOUT+ TXOUT0+/TXOUT0- TXOUT1+/TXOUT1- TXOUT2+/TXOUT2- TXOUT3+/TXOUT3- Figure 13. Typical Panel Clock and Bit Assignment ______________________________________________________________________________________ with LVDS ...
Page 18
... DATA (TXOUT3_) channel for 350Fs after starting/stopping the forward serial link. The MAX9268 uses the DRS input to set the TXCLKOUT_ frequency. Set DRS high for a TXCLKOUT_ frequency of 6.25MHz to 12.5MHz (4-channel mode), or 8.33MHz to 16.66MHz (3-channel mode). Set DRS low for normal operation with a TXCLKOUT_ frequency of 12.5MHz to 78MHz (4-channel mode ...
Page 19
... By default, CNTL2/MCLK operates as a con- trol data output, and MCLK is turned off. Set MCLKDIV (MAX9268 register 0x12, D[6:0 nonzero value to enable the MCLK output. Set MCLKDIV to 0x00 to disable MCLK and set CNTL2/MCLK as a control data output ...
Page 20
... C by the serializer synchronize with the host UART data rate automatically. If the INT or MS inputs of the MAX9268 toggle while there is control-channel communication, the control-channel com- munication can be corrupted since INT has priority on the control channel. In the event of a missed acknowledge, the ...
Page 21
... GMSL SERIALIZER/MAX9268 PERIPHERAL UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 0) GMSL SERIALIZER/MAX9268 SYNC FRAME DEVICE REGISTER ADDRESS GMSL SERIALIZER/MAX9268 PERIPHERAL MASTER TO SLAVE Figure 20. Format Conversion between GMSL UART and I ______________________________________________________________________________________ with LVDS System Interface 1 UART FRAME FRAME 2 ...
Page 22
... The INT pin of the GMSL serializer is the interrupt output and the INT pin of the MAX9268 is the interrupt input. The interrupt output on the GMSL serializer follows the Bypass Mode transitions at the interrupt input, even during reverse- channel communication or loss of lock ...
Page 23
... MAX9268 support spread spectrum. Turning on spread spectrum on the GMSL serializer spreads the serial data and the MAX9268 outputs. Do not enable spread for both the GMSL serializer and the MAX9268. The two select- able spread-spectrum rates at the MAX9268 outputs are Q2% and Q4% (Table 7) ...
Page 24
... MAX9268. The MAX9268 exits sleep mode after locking to the serial data and sets SLEEP = 0. If after 8ms the MAX9268 does not lock to the input serial data, the deserializer goes back to sleep and the internal sleep bit remains set (SLEEP = 1). ...
Page 25
... Both devices power up in normal mode with the serial link disabled. Set SEREN = 1 or CLINKEN = 1 in the GMSL serializer to start the serial link. MAX9268 starts in sleep mode. Link autostarts upon GMSL serializer power-up. Use this case when the MAX9268 powers up before the serializer ...
Page 26
... LVDS System Interface Image-Sensing Applications For image-sensing applications, connect the FC to the MAX9268 and set CDS = high for both the GMSL serial- izer and the MAX9268. The deserializer powers up nor- mally (SLEEP = 0) and continuously tries to lock to a valid serial input. Table 10 summarizes both startup cases, based on the state of the GMSL serializer AUTOS pin ...
Page 27
... D5) first in the GMSL serializer and then the MAX9268 to start the PRBS test. Set PRBSEN = 0 (0x04 D5) first in the MAX9268 and then the GMSL serializer to exit the PRBS self-test. The MAX9268 uses an 8-bit register (0x0E) to count the number of detected errors. The control link also controls the start and stop of the error counting ...
Page 28
... Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Programming the Device Addresses Both the GMSL serializer and the MAX9268 have program- mable device addresses. This allows multiple GMSL devic- es along with peripherals to coexist on the same control channel. The serializer device address is stored in registers 0x00 of each device, while the deserializer device address is stored in register 0x01 of each device ...
Page 29
... Figure 24. Human Body Model ESD Test Circuit ______________________________________________________________________________________ with LVDS System Interface Board Layout The MAX9268 ESD tolerance is rated for Human Body Model, IEC 61000-4-2, and ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic systems. CML/LVDS I/O are tested for ISO 10605 ESD protection and IEC 61000-4-2 ESD protection ...
Page 30
Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Table 12. Register Table (see Table 1) REGISTER BITS NAME ADDRESS D[7:1] SERID 0x00 D0 — D[7:1] DESID 0x01 D0 — D[7: — D4 AUDIOEN 0x02 D[3:2] PRNG D[1:0] ...
Page 31
Gigabit Multimedia Serial Link Deserializer Table 12. Register Table (see Table 1) (continued) REGISTER BITS NAME ADDRESS D7 LOCKED D6 OUTENB D5 PRBSEN D4 SLEEP 0x04 D[3:2] INTTYPE D1 REVCCEN D0 FWDCCEN D7 I2CMETHOD D[6:5] HPFTUNE D4 PDHF 0x05 D[3:0] ...
Page 32
Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Table 12. Register Table (see Table 1) (continued) REGISTER BITS NAME ADDRESS D7 — D6 AUTORST D5 DISINT D4 INT 0x06 D3 GPIO1OUT D2 GPIO1 D1 GPIO0OUT D0 GPIO0 0x07 D[7:0] ...
Page 33
... CNTL1 forced low 0 Serial-data bit 27 is mapped to RES 1 RES bit forced low 00 1.75mA LVDS current 01 3.5mA LVDS current 10 Do not use 11 7mA LVDS current Device identifier 00000100 (MAX9268 = 0x04) 000 Reserved 0 Not HDCP capable 1 HDCP capable XXXX Device revision DEFAULT VALUE ...
Page 34
... RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 48 TQFP-EP Typical Application Circuit TCLKOUT+/- RXCLK+/- RX0+/- TXOUT0+/- TO RX2+/- TO TXOUT2+/- CDS MAX9268 DISPLAY TO PERIPHERALS INT IN+ RX/SDA IN- TX/SCL 50kI SCL SDA LOCK WS WS ...
Page 35
... Added Patent Pending to Features Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2011 Maxim Integrated Products © ...