MAX9268 Maxim, MAX9268 Datasheet - Page 19

• Manufacturer Part Number: MAX9268
• Description: The MAX9268 deserializer utilizes Maxim's gigabit multimedia serial link (GMSL) technology
• Manufacturer: Maxim

synchronous with TXCLKOUT_. The MAX9268 deserial-
izer decodes the audio stream and stores audio words
in a FIFO. Audio rate detection uses an internal oscillator
to continuously determine the audio data rate and output
the audio in I
default. When the audio channel is disabled, the audio
data input (SD) on the serializer becomes a control input
(CNTL0) and SD/CNTL0 becomes a control output on
the deserializer.
Low TXCLKOUT_ frequencies limit the maximum
audio sampling rate. Table 4 lists the maximum audio
sampling rate for various TXCLKOUT_ frequencies.
Spread-spectrum settings do not affect the I
or WS clock frequency.
Some audio DACs such as the MAX9850 do not require
a synchronous main clock (MCLK), while other DACs
require MCLK to be a specific multiple of WS. If the audio
DAC chip needs the MCLK to be a multiple of WS, use
an external PLL to regenerate the required MCLK from
WS or SCK.
For audio applications that have WS synchronous to
TXCLKOUT_, the MAX9268 provides a divided clock
Table 4. Maximum Audio WS Frequency (kHz) for Various TXCLKOUT_ Frequencies
Table 5. f
(REGISTER 0x12, D7)
MCLKSRC SETTING
LENGTH
WORD
(BITS)
16
18
20
24
32
8
0
1
SRC
2
Gigabit Multimedia Serial Link Deserializer
S format. The audio channel is enabled by
> 192
> 192
185.5
174.6
152.2
123.7
______________________________________________________________________________________
12.5
Settings
Additional MCLK Output for
DATA-RATE SETTING
TXCLKOUT_ FREQUENCY
> 192
> 192
> 192
> 192
182.7
148.4
High speed
15
Low speed
Audio Applications
(DRS = LOW)
—
(MHz)
> 192
> 192
> 192
> 192
> 192
164.3
16.6
2
S data rate
with LVDS System Interface
BUS-WIDTH SETTING
3-channel mode
4-channel mode
3-channel mode
4-channel mode
> 192
> 192
> 192
> 192
> 192
> 192
> 20
output on CNTL2/MCLK at the expense of one less
control line in 4-channel mode (3-channel mode is not
affected). By default, CNTL2/MCLK operates as a con-
trol data output, and MCLK is turned off. Set MCLKDIV
(MAX9268 register 0x12, D[6:0]) to a nonzero value
to enable the MCLK output. Set MCLKDIV to 0x00 to
disable MCLK and set CNTL2/MCLK as a control data
output.
The output MCLK frequency is:
where:
Choose MCLKDIV values such that f
greater than 60MHz. MCLK frequencies derived from
TXCLKOUT_ (MSCLKSRC = 0) are not affected by
spread-spectrum settings in the MAX9268. However,
enabling spread spectrum in the GMSL serializer intro-
duces spread spectrum into MCLK. Spread-spectrum
settings of either device do not affect MCLK frequencies
derived from the internal oscillator. The internal oscilla-
tor frequency ranges from 100MHz to 150MHz over all
process corners and operating conditions.
—
f
MCLKDIV = the divider ratio from 1 to 127
SRC
> 192
> 192
185.5
174.6
152.2
123.7
6.25
= the MCLK source frequency (Table 5)
TXCLKOUT_ FREQUENCY
MCLK SOURCE FREQUENCY (f
f
MCLK
> 192
> 192
> 192
> 192
182.7
148.4
7.5
(DRS = HIGH)
=
MCLKDIV
(MHz)
Internal oscillator
3 x f
4 x f
6 x f
8 x f
(120MHz, typ)
f
SRC
TXCLKOUT_
TXCLKOUT_
TXCLKOUT_
TXCLKOUT_
> 192
> 192
> 192
> 192
> 192
164.3
8.33
MCLK
> 192
> 192
> 192
> 192
> 192
> 192
> 10
SRC
is not
)
19