MAX9451 Maxim, MAX9451 Datasheet
MAX9451
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MAX9451 Summary of contents
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... The MAX9450/MAX9451/MAX9452 clock generators provide high-precision clocks for timing in SONET/SDH systems or Gigabit Ethernet systems. The MAX9450/ MAX9451/MAX9452 can also provide clocks for the high- speed and high-resolution ADCs and DACs in 3G base stations. Additionally, the devices can also be used as a jitter attenuator for generating high-precision CLK signals. ...
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... Storage Temperature Range .............................-65°C to +165°C Maximum Junction Temperature .....................................+150°C + 0.3V Operating Temperature Range ...........................-40°C to +85°C DD Lead Temperature (soldering, 10s) .................................+300°C ESD Protection Human Body Model (R = 1.4V to 1.6V for MAX9451 -40°C to +85°C. Typical values at V DDQ A = +25°C, unless otherwise noted.) A SYMBOL CONDITIONS ...
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... MAX9450 Output clock I frequency = MAX9451 CC1 155MHz MAX9452 MAX9450 Output clock I frequency = MAX9451 CC2 155MHz (MAX9450) MAX9452 = 1.4V to 1.6V for MAX9451, T DDQ 3.3V and V = 1.5V for MAX9451 DDQ DDQ SYMBOL CONDITIONS f Measured at IN0 or IN1 IN f Measured at CLK0 or CLK1 OUT C = 8pF (Note 2) L ...
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... Data Setup Time SCL Clock-Low Period SCL Clock-High Period Maximum Receive SCL/SDA Rise Time Minimum Receive SCL/SDA Rise Time Maximum Receive SCL/SDA Fall Time Minimum Receive SCL/SDA Fall Time Fall Time of SDA, Transmitting Pulse Width of Suppressed Spike Capacitive Load for Each Bus Line SERIAL SPI INTERFACE TIMING CHARACTERISTICS ( 2.4V to 3.6V -40° ...
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3.3V +25°C, unless otherwise noted.) DD DDA DDQ A V AND V SUPPLY CURRENT DD DDA vs. VOLTAGE (MAX9450 +25° -40° ...
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... Clock-Output Power Supply. Connect a 2.4V to 3.6V power supply Connect a 1.5V power supply to V DDQ GND. CLK0-, Differential Clock Output 0. The MAX9450 features LVPECL outputs. The MAX9451 features HSTL outputs 19, 20 CLK0+ and the MAX9452 features LVDS outputs. 21 GND Digital GND CLK1-, Differential Clock Output 1 ...
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... The MAX9450/ MAX9451/MAX9452 also provide holdover in case no input clock is supplied. The MAX9450/MAX9451/MAX9452 contain eight 8-bit control registers named CR0 to CR7. The registers are accessible through the I frequency-dividing factor, P ...
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... After changing the dividing ratio, the output clocks complete the current cycle and stay logic-low until the rising edges of the newly divided clock. When CR5[7] is high, the MAX9450/MAX9451/ MAX9452 set all the outputs to logic-low. Setting the bits CR5[6] and CR5[5] properly enables and disables the outputs individually ...
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... CR7 is given in Table 9. If one of the inputs is disabled according to the bits in CR5[3:2], then the mon- itor is disabled. The response of the MAX9450/MAX9451/MAX9452 to a detected input failure depends on the setting of the revert function. If the failed input recovers from the failure, INT and CR7[5:6] resets to zero if revert is acti- vated ...
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... C port has a 7-bit device address. This 7-bit address is the slave (MAX9450/MAX9451/MAX9452) ID for the master to write and read. In the MAX9450/ MAX9451/MAX9452, the first 4 bits (1101) of the address are hard coded into the device at the factory. x 12kHz See Table 3. The last 3 bits of the address are input programmable by the three-level AD0 and AD1 ...
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... Then it sends the byte of device address + R to the slave. The slave (MAX9450/ MAX9451/MAX9452) responds with the content bytes from the registers, starting from the pointed register to the last register, CR8, consecutively back to the master (Figures 5 and 6) ...
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... In Table 4, the register address mapping is still valid, except the first address bit on the left is not used. D14 is the MSB of the address, and D7 is the MSB of the data. D15–D0 are sent with MSB (D15) first. The maximum SCL frequency is 2MHz CSS ...
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Table Address Setting by AD0 and AD1 AD0 AD1 Low Low Low Open Low High Open Low Open Open Open High High Low High Open High High 2 Table and SPI Register Address* ...
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High-Precision Clock Generators with Integrated VCXO Table 8. Control Registers and Control Functions CR5, CR6 FUNCTION 0: Outputs are enabled CR5[7] Output disable 1: Outputs disabled to logic-low 0: CLK0 is disabled to high impedance (overrides CR5[ setting) ...
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... Applications Information Crystal Selection The MAX9450/MAX9451/MAX9452 internal VCXO cir- cuitry requires an external crystal. The frequency of the crystal ranges from 15MHz to 160MHz, depending on the application important to use a quartz crystal that prevents reduction of the frequency pulling range, temperature stability, or excessive output phase jitter. ...
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... High-Precision Clock Generators with Integrated VCXO (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 16 ______________________________________________________________________________________ Package Information PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm, EP OPTION 1 21-0079 F 2 ...
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... For the latest package outline information go to www.maxim-ic.com/packages.) ______________________________________________________________________________________ High-Precision Clock Generators with Integrated VCXO Package Information (continued) PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm, EP OPTION 2 21-0079 ...
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... Fixed typo in crystal frequency range (Functional Diagram) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...