74LVTH16244MTDX Fairchild Semiconductor, 74LVTH16244MTDX Datasheet
74LVTH16244MTDX
Specifications of 74LVTH16244MTDX
74LVTH16244MTDXTR
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74LVTH16244MTDX Summary of contents
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... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 2) Note 1: Ordering code “G” indicates Trays. Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2005 Fairchild Semiconductor Corporation Features Input and output interface capability to systems ...
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Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) Logic Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Inputs (Active LOW –I Inputs –O Outputs 0 15 ...
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Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage I V Output Voltage Input Diode Current Output Diode Current Output Current Supply Current per ...
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DC Electrical Characteristics Symbol Parameter I Power Supply Current CCH I Power Supply Current CCL I Power Supply Current CCZ I Power Supply Current CCZ ' I Increase in Power Supply Current CC (Note 8) Note 5: Applies to ...
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Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide www.fairchildsemi.com Package Number MS48A 6 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...