IDT74FCT162511CTPVG8 IDT, Integrated Device Technology Inc, IDT74FCT162511CTPVG8 Datasheet

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IDT74FCT162511CTPVG8

Manufacturer Part Number
IDT74FCT162511CTPVG8
Description
IC REGISTERD TRCVR 16BIT 56SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
74FCTr
Datasheet
1.IDT74FCT162511CTPAG8.pdf (10 pages)

Specifications of IDT74FCT162511CTPVG8

Logic Type
Registered Transceiver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
16
Current - Output High, Low
24mA, 24mA
Voltage - Supply
5V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74FCT162511CTPVG8
800-1593-2
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical t
• Low input and output leakage ≤ ≤ ≤ ≤ ≤ 1µA (max)
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
• V
• Balanced Output Drivers:
• Series current limiting resistors
• Generate/Check, Check/Check modes
• Open drain parity error allows wire-OR
• Available in the following packages:
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
© 2009 Integrated Device Technology, Inc.
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
machine model (C = 200pF, R = 0)
– ±24mA (industrial)
– ±16mA (military)
– Industrial: SSOP, TSSOP
– Military: CERPACK
CC
= 5V ±10%
sk(o)
(Open Drain)
ODD/EVEN
(Output Skew) < 250ps, clocked mode
GEN/CHK
CLKAB
PA1,2
OEBA
A0-15
PERA
LEAB
Parity, data
Byte
Parity
Generator/
Checker
18
FAST CMOS 16-BIT
REGISTERED/LATCHED
TRANSCEIVER WITH PARITY
Data
16
Parity
2
Latch/
Register
Latch/
Register
1
DESCRIPTION:
using advanced dual metal CMOS technology. This high-speed, low-power
transceiver combines D-type latches and D-type flip-flops to allow data flow in
transparent, latched, or clocked modes. The device has a parity generator/
checker in the A-to-B direction and a parity checker in the B-to-A direction. Error
checking is done at the byte level with separate parity bits for each byte. Separate
error flags exits for each direction with a single error flag indicating an error for
either byte in the A-to-B direction and a second error flag indicating an error for
either byte in the B-to-A direction. The parity error flags are open drain outputs
which can be tied together and/or tied with flags from other devices to form a single
error flag or interrupt. The parity error flags are enabled by the OExx control
pins allowing the designer to disable the error flag during combinational
transitions.
direction while LEBA, CLKBA, and OEBA control the B-to-A direction. GEN/
CHK is only for the selection of A-to-B operation. The B-to-A direction is always
in checking mode. The ODD/EVEN select is common between the two directions.
Except for the ODD/EVEN control, independent operation can be achieved
between the two directions by using the corresponding control lines.
The FCT162511T 16-bit registered/latched transceiver with parity is built
The control pins LEAB, CLKAB, and OEAB control operation in the A-to-B
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
Byte
Parity
Checking
Parity, Data
Parity, data
18
IDT54/74FCT162511AT/CT
18
SEPTEMBER 2009
(Open Drain)
OEAB
B0-15
PB1,2
PERB
LEBA
CLKBA
DSC-2916/4

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IDT74FCT162511CTPVG8 Summary of contents

Page 1

IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER FEATURES: • 0.5 MICRON CMOS Technology • Typical t (Output Skew) < 250ps, clocked mode sk(o) • Low input and output leakage ≤ ≤ ≤ ≤ ≤ 1µA (max) • ESD > 2000V per ...

Page 2

IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER BLOCK DIAGRAM ODD/EVEN OEAB LEBA CLKBA CLKAB LEAB OEBA GEN/CHK PERA (Open Drain ...

Page 3

IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER PIN CONFIGURATION OEAB 1 LEAB GND ...

Page 4

IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER (1, 4) FUNCTION TABLE Inputs OEAB LEAB CLKAB ↑ ↑ NOTES: 1. A-to-B data flow ...

Page 5

IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial –40°C to +85° 5.0V ±10%; Military Symbol Parameter V Input HIGH Level IH V ...

Page 6

IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER POWER SUPPLY CHARACTERISTICS Symbol Parameter ΔI Quiescent Power Supply Current CC TTL Inputs HIGH I Dynamic Power Supply CCD (4) Current (6) I Total Power Supply Current C NOTES: 1. For conditions shown as ...

Page 7

IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER SWITCHING CHARACTERISTICS OVER OPERATING RANGE (PROPAGATION DELAYS) Symbol Parameter t Propagation Delay, PAx to PBx PLH Ax, PBx to PAx PHL GEN/CHK LOW t Propagation Delay PLH ...

Page 8

IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER SWITCHING CHARACTERISTICS OVER OPERATING RANGE (SET UP TIMES) Symbol Parameter GEN/CHK LOW t Set-up Time SU HIGH or LOW GEN/CHK HIGH Ax to CLKAB GEN/CHK HIGH t Set-up Time SU PAx to CLKAB t ...

Page 9

IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER TEST CIRCUITS AND WAVEFORMS Pulse D.U.T. Generator R T Test Circuits for All Outputs DATA INPUT t SU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR ...

Page 10

IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER ORDERING INFORMATION XX FCT XXX Temp. Range Family Device Type Datasheet Document History 09/06/09 Pg.6 Updated the ordering information by removing the "IDT" notation and non RoHS part. CORPORATE HEADQUARTERS 6024 Silver Creek Valley ...

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