TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 6

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

(TB0IN0, INT6, RXD1, RXD0) PP4
(TA7OUT, INT5, TXD1, TXD0) PP3
(SCLK1, SCLK0,
(
(AN3, MY, ADTRG ) PG3
(AN0 to AN1) PG0 to PG1
(AN4 to AN5) PG4 to PG5
CTS ,
(TA1OUT, MLDALM) PM1
(LGOE2 to 0)PK7 to PK5
( SDCAS , SRLUB ) PJ1
(LD15 to 8) PT7 to PT0
( SDRAS , SRLLB ) PJ0
(CLKOUT, LDIV) PX4
( SDWE , SRWR ) PJ2
0
(LD7 to 0)PL7 to PL0
CTS , SCLK1,SCLK0)
(RXD1, RXD0) P91
(TA2IN, INT3) PC3
(TA0IN, INT1) PC1
(TXD1, TXD0) P90
(X1D4, X1USB) PX
(SDLUDQM) PJ4
CTS
VREFH, VREFL
(SDLLDQM) PJ3
(I2S0CKO) PF0
(TB0OUT0) PP6
(AN2, MX) PG2
(PX, INT4) P96
1
(LHSYNC) PK4
(LVSYNC) PK3
(I2S0WS) PF2
(I2S0DO) PF1
0
(SDCKE) PJ7
AVCC, AVSS
(LLOAD) PK1
(SDCLK) PF7
( SPCS ) PR2
(SPCLK) PR3
,
(SPDO) PR1
CTS
(LCP0) PK0
(SPDI) PR0
(LFR) PK2
(PY) P97
(SDA) PV6
1
(SCL) PV7
TB1IN0, INT7)
P92
D+
D -
PP5
Touch Screen
SBI (I
10-bit 6ch
Converter
Controller
Controller
Controller
Serial I/O
16bit timer
16bit timer
Controller
SDRAM
8bit timer
(TMRA0)
8bit timer
8bit timer
8bit timer
8bit timer
8bit timer
8bit timer
8bit timer
(TMRA1)
(TMRA2)
(TMRA3)
(TMRA4)
(TMRA5)
(TMRA6)
(TMRA7)
(TMRB0)
(TMRB1)
(I
SIO0
LCD
(TSI)
USB
SPI
AD
I
2
I/F
2
S0)
2
S
Cbus)
Figure 1.1 Block Diagram of TMP92CF29A
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
WATCH-DOG TIMER
BOOT ROM 8KB
144KB RAM
SR
92CF29A-4
32bit
DMAC
P C
MMU
MAC
W
B
D
H
SP
IX
IY
IZ
A
C
E
L
F
Clock gear
ALARM-OUT
KEY-BOARD
NAND-FLASH
Controller
MELODY/
H-OSC
Interrupt
L-OSC
PORT1
PORT4
PORT5
PORT6
PORT7
PORTC
PORT8
I/F (2ch)
PLL
PMC
RTC
I/F
TMP92CF29A
DVCC3A [8]
DVCC1A [4]
DVCC1B [1]
DVSSCOM [8]
PC4 (EA26, SPDI)
PC5 (EA27, SPDO)
PC6 (EA28, SPCLK)
DVCC1C [1]
DVSS1C [1]
RESET
AM [1:0]
D0 to D7
P10 to P17 (D8 to D15)
P60 to P67 (A16 to A23)
X1
X2
XT1
XT2
P40 to P47 (A0 to A7)
P50 to P57 (A8 to A15)
P70 ( RD )
P73 (EA24)
P74 (EA25)
P75(R/ W , NDR/ B )
P76 ( WAIT )
P71 ( WRLL , NDRE )
P72 (
P86 ( CSZD ,
P87 ( CSXB ,
PJ5 (NDALE)
PJ6 (NDCLE)
PA0 to PA7 (KI0 to KI7)
PN0 to PN7 (KO0 to KO7)
PC7 (KO8)
PM7 (PWE)
P80 (
P81 (
P82 (
P83 (
PM2 ( ALARM , MLDALM )
PC0 (INT0)
PC2 (INT2)
2009-06-11
WRLU
CS )
CS , SDCS )
CS , CSZA , SDCS )
CS , CSXA )
1
0
2
3
ND
ND
, NDWE )
1
0
CE
CE
)
)