TLE 6711G Infineon Technologies, TLE 6711G Datasheet - Page 13

• Manufacturer Part Number: TLE 6711G
• Manufacturer: Infineon Technologies

Specifications of TLE 6711G

• Packages: PG-DSO-14
• Comment: -
• Vq (max): 5.0V
• Iq (max): 250.0 mA
• Iq (typ): 1,500.0 µA
• Output: Boost/Buck Conv.

4.3.1
For supervision of the Boost output voltage an open drain DMOS output is used. The output is high impedance in
normal operation and low during the warning.
The OVL goes LOW if the PWM comparator output (see
when the Error-Signal falls below the minimum value of the Error-Ramp, this mean that Boost voltage falls below
a certain threshold voltage.
The OVL output used as a warning for insufficient Boost voltage.
4.4
A stabilized logic supply voltage (typ. 5 V) for general purpose is realized in the system by a buck converter. An
external buck-inductance
frequency (pin R).
The buck regulator supply is given by the boost converter output
stored energy of the boost converter capacitor is used.
Like the boost converter, the buck converter uses the temperature compensated bandgap reference voltage
(typ. 2.8 V) for its regulation loop.
This reference voltage is connected to the non-inverting input of the error amplifier and an internal voltage divider
supplies the inverting input. Therefore the output voltage
The output of the error amplifier goes to the inverting input of the PWM comparator as well as to the buck
compensation output BUC.
When the error amplifier output voltage exceeds the sawtooth voltage the output power MOS-transistor is switched
on. So the duration of the output transistor conduction phase depends on the
variable pulse width is generated.
Figure 10
Data Sheet
BUC
Pin 6
V
Pin 7
R
Pin 1
CC
R
R
22k
28k
VCC1
VCC2
V
Oscillator
V
CC
V
GND
max
Boost Status Output OVL
Buck Converter
Buck Converter Block Diagram
min
200
R
Prot1
GND
t t
r
=
f
V
2.8 V
t
r
REF
Error
AMP
-
+
t
Ramp
L
Error-
Signal
Error-
Ramp
BU
Schmitt-trigger 1
is PWM switched by a high side DMOS power transistor with the programmed
V
V
39.7k
10.3k
high
PWM
COMP
low
R
R
-
+
VCC3
VCC4
GND
t t
V
r f
H when
Error-Signal
<
Error-Ramp
CC
t
L when
T
r
GND
j
> 175 ˚C
=
t
V
1.2 V
thOV
OV
COMP
Clock
+
-
L when
Overcurrent
Output Stage
OFF when H
R
S
H when
OV at
Error-FF
&
&
V
CC
Q
Q
13
Figure
OFF when H
V
CC
H when
UV at
is fixed due to the internal resistor ratio to typ. 5.0 V.
NOR 1
8) remains HIGH for clock time period. This occurs
V
1
Boost
UV
COMP
V
NAND 2
BOOST
-
+
&
GND
=
R
S
, in case of a battery power-down the
V
4 V
thUV
PWM-FF
&
&
L when
Overcurrent
V
CC
Q
Q
H =
OFF
level. A logic signal PWM with
OC
COMP
INV
1
-
+
H =
ON
Rev. 3.4, 2007-08-16
Circuit Description
Supply
Boost
Driver
Gate
Driver
V
18 mV
thOC
TLE 6711
Power
D-MOS
18 m
R
AEB02947
Sense
V
Pin 9
BDS
Pin 10
BUO
Pin 8
Boost