TLE 6711G Infineon Technologies, TLE 6711G Datasheet - Page 8

• Manufacturer Part Number: TLE 6711G
• Manufacturer: Infineon Technologies

Specifications of TLE 6711G

• Packages: PG-DSO-14
• Comment: -
• Vq (max): 5.0V
• Iq (max): 250.0 mA
• Iq (typ): 1,500.0 µA
• Output: Boost/Buck Conv.

4
Below some important sections of the TLE 6711 G/GL are described in more detail.
4.1
In order to avoid any system failure, a sequence of several conditions has to be passed. In case of
down (
When the level of
time
reaction time
reaction time
Figure 4
4.2
The watchdog uses one hundred of the oscillator’s clock signal period as a timebase, defined as the watchdog
cycle time
After power-on, the reset output signal at the RO pin (microcontroller reset) is kept LOW for the reset delay time
t
t
shown below. After the closed window the open window with the duration
at minimum until the trigger process has occurred, at maximum
A HIGH to LOW transition of the watchdog trigger signal on pin WDI is taken by a trigger. To avoid wrong triggering
due to parasitic glitches two HIGH samples followed by two LOW samples (sample period
valid trigger. If a trigger signal appears at the watchdog input pin WDI during the open window or a power up/down
occurs, the watchdog window signal is reset and a new closed window follows.
A reset is generated (RO goes LOW) if there is no trigger pulse during the open window or if a pretrigger occurs
during the closed window. This reset happens after 64 cycles after the latest valid closed window start time and
lasts for further 64 cycles.
The triggering is correct also, if the first three samples (two HIGH one LOW) of the trigger pulse at pin WDI are
inside the closed window and only the fourth sample (the second LOW sample) is taken in the open window.
In addition to the microcontroller reset signal RO the device generates a system enable signal at pin SEN. If RO
Data Sheet
RD
CW
, i.e. 64 cycles. With the LOW to HIGH transition of the signal at RO the device starts the closed window time
= 32 cycles. A trigger signal within this window is interpreted as a pretrigger failure according to the figures
t
RD
V
CC
before switching to HIGH. If
Power
t
<
CYL
V
RO
Circuit Description
Power On Reset
V
Reset Function
Watchdog Operation
CC
V
t
t
RT
RR
.
H
RR
L
RT
, the reset circuit is activated and a power down sequence of period
avoids wrong triggering caused by short “glitches” on the
V
typ. 4.65 V
1 V
Invalid
for
Start-Up
CC
Start-Up
t
reaches the reset threshold
>
t
RR
) a logic LOW signal is generated at the pin RO to reset an external microcontroller.
ON Delay
t
RD
Normal
V
CC
<
drops below the reset threshold
t
RR
V
RT
, the signal at RO remains LOW for the Power-up reset delay
t
8
RR
Failed
ON Delay
Started
Invalid
t
OW
is 32 cycles.
<
N
t
RD
V
t
OW
CC
V
-line.
ON Delay
is started. The open window lasts
RT
Stopped
Invalid
Failed
for a time extending the reset
t
RD
t
CYL
is initiated. The reset
Rev. 3.4, 2007-08-16
Circuit Description
t
Normal
RD
) are decoded as a
AET02950
TLE 6711
V
CC
t
t
power