TLE 7810G Infineon Technologies, TLE 7810G Datasheet - Page 20

• Manufacturer Part Number: TLE 7810G
• Manufacturer: Infineon Technologies

Specifications of TLE 7810G

• Packages: PG-DSO-28
• Flash: 16.0 kByte
• Frequency (f): 24.0 MHz
• High Side Switch: 1
• High Voltage Monitor Input: 5
• Gpio: 8

8
Control and status information between SBC and μC is exchanged via a digital interface, that is called “serial
peripheral interface” (SPI) on the SBC side, and “synchronous serial channel” (SSC) on the μC side. The 16-bit
wide Programming or Input Word of the SBC (see
first”), which is synchronized with the clock input CLK supplied by the μC. The Diagnosis or Output Word appears
synchronously at the data output DO (see
The transmission cycle begins when the chip is selected by the Chip Select Not input CSN (“low” active). After the
CSN input returns from L to H, the word that has been read in becomes the new control word. The DO output
switches to tri-state status at this point, thereby releasing the DO bus for other usage.
The state of DI is shifted into the input register with every falling edge on CLK. The state of DO is shifted out of
the output register after every rising edge on CLK. The number of received input clocks is supervised by a modulo-
16 operation and the Input/Control Word is discarded in case of a mismatch.
This error is flagged by a “high” at the data output pin DO (interconnect to μC: P1.4) of the following SPI output
word before the first rising edge of the clock is received. Additionally the logic level of DO will be “OR-ed” with the
logic level of DI (P1.3).
Note: After wake-up from low-power modes the device needs to be set to Active Mode first before switches like
Figure 10
Data Sheet
Input
Data
LS1, LS2, Supply Output and LED Driver can be turned on with the second SPI command.
SPI (Serial Peripheral Interface)
On/Off
16-Bit SPI Input Data / Control Word
MSB
15 14 13 12 11 10
WD
On/Off
Meas.
I/F
Vtemp*
Vbat/
Reserved
ADC
On/Off*
MON5
Reserved
Reserved
Configuration Registers
On/Off*
MON4
0**
** if bit set to „1" command will be ignored
* remains unchanged after Vcc-UV or WD-RESET
On/Off*
MON3
Table
(Watchdog Trigger Register )
Window Watchdog Timing
On/Off
On/Off*
MON2
LS2
9).
9
Bit Position: 10 .. 5
Table 2
Cyclic Wake Timing*
Bit Position: 9 .. 5
On/Off
On/ Off*
MON1
LS1
8
20
HS-LED
10.4k*
disable
OV/UV
to
LIN
7
Table
HS-LED
Delay*
Reset
On /Off
6
8) is read in via the data input DI (with “LSB
Thres*
Reset
Supply
Output
On/Off
5
Configuration
CS1
4
10
11
00
01
SPI (Serial Peripheral Interface)
Select
CS0
3
Mode Selection
MS2
LIN RxD Only
2
Rev. 3.01, 2008-04-15
LIN Sleep
not valid
not valid
not valid
Active
Active
Sleep
Stop
Bits
MS1
1
TLE7810G
LSB
MS0
0
011
101
100
110
111
000
001
010