ADP3180 Analog Devices, ADP3180 Datasheet
ADP3180
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ADP3180 Summary of contents
Page 1
... Power Good output that accommodates on-the-fl y output voltage changes requested by the CPU. ADP3180 is specifi ed over the commercial temperature range of 0°C to 85°C and is available in a 28-lead TSSOP package. *Patent Pending REV. 0 Information furnished by Analog Devices is be lieved to be accurate and reliable ...
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... ADP3180–SPECIFICATIONS Parameter ERROR AMPLIFIER Output Voltage Range Accuracy Line Regulation Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate VID INPUTS Input Low Voltage Input High Voltage Input Current, Input Voltage Low Input Current, Input Voltage High ...
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... Relative to Nominal DAC Output CROWBAR Relative to FBRTN t Overvoltage to PWM Going Low CROWBAR 400 µA OL(PWM) PWM(SINK 400 µA OH(PWM) PWM(SOURCE) V VCC Rising UVLO –3– ADP3180 Min Typ Max 4.7 nF 350 0.4 0.8 – –200 –250 –325 +90 +150 +200 ...
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... CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily late on the human body and test equipment and can discharge without detection. Although the ADP3180 features proprietary ESD pro tec tion circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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... Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit threshold of the converter. This pin is actively pulled low when the ADP3180 EN input is low or when VCC is below its UVLO threshold to signal to the driver IC that the driver high side and low side outputs should go low. ...
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... ADP3180–Typical Performance Characteristics 100 150 R VALUE – SEE EQUATION 1 FOR FREQUENCIES NOT ON THIS GRAPH TPC 1. Master Clock Frequency vs. R TEST CIRCUITS ADP3180 12V 28 VCC CSCOMP 18 39k 100nF CSSUM 17 1k CSREF 16 1.0V V GND 19 Test Circuit 1. Current Sense Amplifi ...
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... Handling the high currents in a single-phase converter would place high thermal demands on the components in the system such as the inductors and MOSFETs. The multimode control of the ADP3180 ensures a stable, high performance topology for: ∑ Balancing currents and thermals between phases ∑ ...
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... Also, more than one output can time for overlapping phases. Master Clock Frequency The clock frequency of the ADP3180 is set with an external resistor connected from the RT pin to ground. The frequency fol- lows the graph in TPC 1. To determine the frequency per phase, the clock is divided by the number of phases in use ...
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... The latch-off function can be reset either by removing and reap- plying VCC to the ADP3180 or by pulling the EN pin low for a short time. To disable the short circuit latch-off function, the external resistor to ground should be left open, and a high value (> ...
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... UVLO threshold and the EN pin must be higher than its logic threshold for the ADP3180 to begin switching. If UVLO is less than the threshold or the EN pin is a logic low, the ADP3180 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground ...
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... EN CSCOMP 12 DELAY CSSUM 17 C CS1 2.2nF 13 RT CSREF 249k RAMPADJ ILIMIT 14 15 ® 4 CPU Supply Circuit, VRD 10 Design –11– ADP3180 820 F/2. Fujitsu RE Series 600nH/1.6m 8m ESR (each C10 4.7nF C28 C21 R1 2 23MLCC AROUND SOCKET L3 600nH/1.6m C14 4.7nF R2 2 ...
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... ADP3180 Setting the Clock Frequency The ADP3180 uses a fi xed-frequency control architecture. The frequency is set by an external timing resistor (R frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and input and output capacitors. ...
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... TC = 0.0039 Compute the relative values for the layout so standard CS R should PH( –13– ADP3180 and R are needed (see CS1 CS2 PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR TO OR LOW SIDE MOSFET SWITCH R NODES TH R PH1 R R CS1 ...
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... V) are recommended. The maximum output current I (12) requirement for the low side (synchronous) MOSFETs. With the ADP3180, currents are balanced between phases, thus the current in each low side MOSFET is the output current divided by the total number of MOSFETs (n –14– ) ≤ ...
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... Equation 19 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance. –15– ADP3180 = 3), with (max 120ºC) and an Infi neon DS(MF 2370 pF (max) and R = 8.4 mW (max at T DS(SF) ...
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... where, for the ADP3180 the PCB resistance from the bulk capacitors to the ceramics and where R side MOSFET ON resistance per phase. For this example equals 0. approximately 0.6 mW (assuming RT a 4-layer motherboard), and L is 375 pH for the eight Al-Poly X capacitors ...
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... FB Figure 7. Effi ciency of the Circuit of Figure 4 vs. Output Current TUNING PROCEDURE FOR THE ADP3180 1. Build circuit based on compensation values computed from design spreadsheet. 2. Hook up dc load to circuit, turn on and verify operation. Also check for jitter at no-load and full-load. ...
Page 18
... V are equal). DCDRP Since the ADP3180 turns off all of the phases (switches inductors to ground), there is no ripple voltage present during load release. Thus, you do not have to add headroom for ripple, allowing your load release V and still be meeting spec. ...
Page 19
... If critical signal lines (including the output voltage sense lines of the ADP3180) must cross through power circuitry best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. ∑ ...
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... ADP3180 PIN 1 0.15 0.05 COPLANARITY OUTLINE DIMENSIONS 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 9.80 9.70 9. 4.50 4.40 4.30 6.40 BSC 1 14 0.65 1.20 BSC MAX 0.30 0.20 0.19 SEATING 0.09 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AE –20– 0. 0.60 0.45 REV. 0 ...