KSZ8842 Micrel Semiconductor, KSZ8842 Datasheet
KSZ8842
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KSZ8842 Summary of contents
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... KSZ8842, the KSZ8842MQLI, can be ordered Information). The KSZ8842M can be configured as a switch low-latency (d 310 nanoseconds) repeater in latency- critical, embedded or industrial Ethernet applications. For industrial applications, the KSZ8842M can run in half-duplex mode regardless of the application. Functional Diagram ...
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... Available in –16 version for 8/16-bit bus support and – 32 version for 32-bit bus support (see Information). Additional Features In addition to offering all of the features of an integrated Layer-2 managed switch, the KSZ8842M offers: x Repeater mode capabilities to allow for cut through in latency critical industrial Ethernet or embedded Ethernet applications x Dynamic buffer memory scheme – ...
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... 128-Pin LQFP (Available Q4 Samples – +85 C 128-Pin LQFP (Available Q4 Samples) Evaluation Board for the KSZ8842-16MQL City, State/Province, Country San Jose, CA 95131 USA Medford, NJ 08055 USA Richardson, TX 75080 USA San Jose, CA 95131 USA Shenzhen, PR China 518026 Seoul 135-080 Korea Taipei, 11468 Taiwan, R ...
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... Ordering Information ............................................................................................................... 3 Contacts.................................................................................................................................... 3 Revision History....................................................................................................................... 3 Content ..................................................................................................................................... 4 List of Figures .......................................................................................................................... 8 List of Tables............................................................................................................................ 9 Pin Configuration for KSZ8842-16 Switches (8/16-Bit) ....................................................... 10 Pin Description for KSZ8842-16 Switches (8/16-Bit)........................................................... 11 Pin Configuration for KSZ8842-32 Switches (32-Bit) .......................................................... 16 Pin Description for KSZ8842-32 Switches (32-Bit).............................................................. 17 Functional Description .......................................................................................................... 22 Functional Overview: Physical Layer Transceiver.............................................................. 22 100BASE-TX Transmit ...
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... Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR ............................................................................................61 Bank 17 QMU Data Register Low (0x08): QDRL ..............................................................................................................61 Bank 17 QMU Data Register High (0x0A): QDRH ............................................................................................................61 Bank 18 Interrupt Enable Register (0x00): IER.................................................................................................................62 Bank 18 Interrupt Status Register (0x02): ISR..................................................................................................................63 Bank 18 Receive Status Register (0x04): RXSR ..............................................................................................................64 November 2005 KSZ8842-16/32 MQL/MVL 5 Rev. 1.4 ...
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... Bank 48 Port 1 Control Register 3 (0x06): P1CR3............................................................................................................88 Bank 48 Port 1 Ingress Rate Control Register (0x08): P1IRCR........................................................................................89 Bank 48 Port 1 Egress Rate Control Register (0x0A): P1ERCR.......................................................................................91 Bank 49 Port 1 PHY Special Control/Status, LinkMD (0x00): P1SCSLMD .......................................................................93 Bank 49 Port 1 Control Register 4 (0x02): P1CR4............................................................................................................94 November 2005 KSZ8842-16/32 MQL/MVL 6 Rev. 1.4 ...
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... Synchronous Write Timing (VLBUSN = 0) ......................................................................................................................116 Synchronous Read Timing (VLBUSN = 0) ......................................................................................................................117 EEPROM Timing.............................................................................................................................................................118 Auto Negotiation Timing..................................................................................................................................................119 Reset Timing...................................................................................................................................................................120 Selection of Isolation Transformers................................................................................... 121 Selection of Reference Crystal ........................................................................................... 121 Package Information............................................................................................................ 122 Acronyms and Glossary...................................................................................................... 124 November 2005 ............................................................................................. 108 7 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
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... Figure 9. Destination Address Lookup Flow Chart in Stage One ................................................................................................ 27 Figure 10. Destination Address Resolution Flow Chart in Stage Two ......................................................................................... 28 Figure 11. Mapping from ISA-like, EISA-like, and VLBus-like transactions to the KSZ8842M Bus ............................................. 34 Figure 12. KSZ8842M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections ....................................................................................... 34 Figure 13. 802.1p Priority Field Format ....................................................................................................................................... 41 Figure 14 ...
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... Table 31. Synchronous Read Timing Parameters..................................................................................................................... 117 Table 32. EEPROM Timing Parameters.................................................................................................................................... 118 Table 33. Auto Negotiation Timing Parameters......................................................................................................................... 119 Table 34. Reset Timing Parameters .......................................................................................................................................... 120 Table 35. Transformer Selection Criteria................................................................................................................................... 121 Table 36. Qualified Single Port Magnetic .................................................................................................................................. 121 Table 37. Typical Reference Crystal Characteristics ................................................................................................................. 121 November 2005 KSZ8842-16/32 MQL/MVL 9 Rev. 1.4 ...
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... 124 125 126 D 2 127 D 1 128 D 0 Figure 3. Option – KSZ8842-16 MVL 128-Pin LQFP (Top View) November 2005 SZ8842- (Top V iew ) 10 KSZ8842-16/32 MQL/MVL ...
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... Micrel Confidential Pin Description for KSZ8842-16 Switches (8/16-Bit) Pin Pin Name Type Number 1 TEST_EN I 2 SCAN_EN I 3 P1LED2 Opu P1LED1 Opu 4 5 P1LED0 Opu 6 P2LED2 Opu 7 P2LED1 Opu 8 P2LED0 Opu 9 DGND Gnd 10 VDDIO P 11 RDYRTNN Ipd November 2005 Pin Function Test Enable For normal operation, pull-down this pin to ground ...
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... For VLBus-like mode, the falling edge of this signal indicates ready. This signal is synchronous to the bus clock signal BCLK. For burst mode (32-bit interface only), the KSZ8842M drives this pin low to signal wait states. Interrupt Active Low signal to host CPU to indicate an interrupt status bit is set, this pin need an external 4 ...
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... Port 2 physical receive (MDI) or transmit (MDIX) signal (- differential) Port 2 physical receive (MDI)or transmit (MDIX) signal (+ differential) Analog ground Port 2 physical receive (MDI) or transmit (MDIX) signal (- differential) Port 2 physical receive (MDI) or transmit (MDIX) signal (+ differential) 1.2 analog V input power supply from VDDCO (pin24) through external Ferrite DD 13 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
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... BE1N for 8-bit bus mode). No Connect Digital core ground 1.2V digital core V input power supply from VDDCO (pin24) through external DD Ferrite bead and capacitor. 3.3V digital V input power supply for IO with well decoupling capacitors. DDIO No Connect 14 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
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... IO with well decoupling capacitors. DDIO No Connect Data 15 Data 14 Data 13 Data 12 Data 11 Data 10 Data 9 Data 8 Data 7 Data 6 Data 5 Data 4 Data 3 Digital IO ground Digital core ground 3.3V digital V input power supply for IO with well decoupling capacitors. DDIO Data 2 Data 1 Data 0 15 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
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... Figure 4. Standard – KSZ8842-32 MQL 128-Pin PQFP (Top View) D26 97 98 D25 99 D24 100 D23 101 D22 102 D21 103 D20 104 ...
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... Micrel Confidential Pin Description for KSZ8842-32 Switches (32-Bit) Pin Pin Name Type Number 1 TEST_EN I 2 SCAN_EN I 3 P1LED2 Opu 4 P1LED1 Opu 5 P1LED0 Opu 6 P2LED2 Opu 7 P2LED1 Opu 8 P2LED0 Opu 9 DGND Gnd 10 VDDIO P 11 RDYRTNN Ipd November 2005 Pin Function Test Enable For normal operation, pull-down this pin to ground ...
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... For VLBus-like mode, the falling edge of this signal indicates ready. This signal is synchronous to the bus clock signal BCLK. For burst mode (32-bit interface only), the KSZ8842M drives this pin low to signal wait states. Interrupt Active Low signal to host CPU to indicate an interrupt status bit is set, this pin need an external 4 ...
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... Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential) 3.3V analog V input power supply with well decoupling capacitors. DD 3.3V analog V DD Port 2 physical receive (MDI) or transmit (MDIX) signal (- differential) Port 2 physical receive (MDI) or transmit (MDIX) signal (+ differential) Analog ground Port 2 physical receive (MDI) or transmit (MDIX) signal (- differential) 19 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
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... Byte Enable 1 Not, Active low for Data byte 1 enable. Byte Enable 0 Not, Active low for Data byte 0 enable. Data 31 Digital core ground 1.2V digital core V input power supply from VDDCO (pin24) through external DD Ferrite bead and capacitor. 3.3V digital V input power supply for IO with well decoupling capacitors. DDIO 20 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
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... IO with well decoupling capacitors. DDIO Data 16 Data 15 Data 14 Data 13 Data 12 Data 11 Data 10 Data 9 Data 8 Data 7 Data 6 Data 5 Data 4 Data 3 Digital IO ground Digital core ground 3.3V digital V input power supply for IO with well decoupling capacitors. DDIO Data 2 Data 1 Data 0 21 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
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... The KSZ8842M contains two 10/100 physical layer transceivers (PHYs), two MAC units, and a DMA channel integrated with a Layer-2 switch. The KSZ8842M contains a bus interface unit (BIU), which controls the KSZ8842M via an 8, 16, or 32-bit host interface. Physical signal transmission and reception are enhanced through the use of analog circuits in the PHY that make the design more efficient and allow for low power consumption ...
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... Power Management The KSZ8842M features per port power-down mode. To save power, the user can power-down the port that is not in use by setting bit 11 in either P1CR4 or P1MBCR register for port 1 and setting bit 11 in either P2CR4 or P2MBCR register for port 2 ...
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... If auto negotiation is not supported or the link partner to the KSZ8842M is forced to bypass auto negotiation, the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol ...
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... Set Link Mode LinkMD Cable Diagnostics The KSZ8842M LinkMD uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with a maximum distance of 200m and an accuracy of +/– ...
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... If P1VCT[14:13]=11 or P2VCT[14:13]=11, this indicates an invalid test, and occurs when the KSZ8842M is unable to shut down the link partner. In this instance, the test is not run not possible for the KSZ8842M to determine if the detected signal is a reflection of the signal generated or a signal from another source. ...
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... Micrel Confidential Forwarding The KSZ8842M forwards packets using the algorithm that is depicted in the following flowcharts. Figure 9 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “ ...
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... These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors. 2. 802.3x pause frames. The KSZ8842M intercepts these packets and performs the flow control. 3. "Local" packets. Based on destination address (DA) lookup. If the destination port from the lookup table matches the port from which the packet originated, the packet is defined as " ...
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... KSZ8842M issues a flow control frame (Xoff), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KSZ8842M sends out the other flow control frame (Xon) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated ...
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... Since both synchronous and asynchronous signals are independent of each other, synchronous burst transfer and asynchronous transfer can be mixed or interleaved but cannot be overlapped (due to the sharing of the common signals). In terms of physical data bus size, the KSZ8842M supports 8, 16, and 32 bit host/industrial standard data bus sizes. November 2005 ...
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... Micrel Confidential Given a physical data bus size, the KSZ8842M supports 8, 16, or 32-bit data transfers depending on the size of the physical data bus. For example, for a 32-bit system/host data bus, it allows 8, 16, and 32-bit data transfers (KSZ8842- 32MQL); for a 16-bit system/host data bus, it allows 8 and 16-bit data transfers (KSZ8842-16MQL); and for 8-bit system/host data bus, it only allows 8-bit data transfers (KSZ8842-16MQL) ...
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... EISA-like bus (non-burst) interface as shown in the Figure 17. This type of interface requires ADSN to latch the address on the rising edge. The BIU decodes latched A[15:4] and qualifies with AEN to determine if the KSZ8842M switch is the intended target. The data transfer is the same as the first case. ...
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... The M/nIO signal connection in VLBus is routed to AEN. The CYCLEN in this application is used to sample the SWR signal when it is asserted. Usually, CYCLEN is one clock delay of ADSN. There is a handshaking process to end the cycle of VLBus-like transfers. When the KSZ8842M is ready to finish the cycle ...
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... Figure 12. KSZ8842M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections BIU Implementation Principles Since the KSZ8842M is an I/O device with 16 addressable locations, address decoding is based on the values of A15-A4 and AEN. Whenever DATACSN is asserted, the address decoder is disabled and a 32-bit transfer to Data Register is assumed (BE3N – BE0N are ignored). ...
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... The EISA-like burst transfer is supported using synchronous interface signals and DATACSN when I/O signal VLBUSN = 1. Both the system/host/memory and KSZ8842M are capable of inserting wait states. To set the system/host/memory to insert a wait state, assert RDYRTNN signal. To set the KSZ8842M to insert a wait state, assert SRDYN signal. ...
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... On transmit, all bytes are provided by the CPU, including the source address. The KSZ8842M does not insert its own source address. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the KSZ8842M treated transparently as data for transmit operations. ...
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... Table 8 gives the format of the RX byte count field. Bit Description 15-11 Reserved 10-0 RXBC Receive Byte Count Receive Byte Count. November 2005 Table 7. FRXQ Packet Receive Status Table 8. FRXQ RX Byte Count Field 37 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
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... BPDU packets). The “overriding” bit is set so that the switch forwards those specific packets to the processor. The processor can send packets to the port(s) in this state. Address learning is enabled on the port in this state. Table 9: Spanning Tree States 38 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
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... SGCR2, bit 8 to “1”. For example, port 1 is programmed to be “receive sniff”, port 2 is programmed to be “transmit sniff”, and the host port is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8842M forwards the packet to both port 2 and the host port. ...
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... The KSZ8842M supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification. KSZ8842M provides a 16-entry VLAN table, which converts the 12-bits VLAN ID (VID) to the 4-bits Filter ID (FID) for address lookup non-tagged or null-VID-tagged packet is received, the ingress port default VID is used for lookup. In VLAN mode, the lookup process starts with VLAN table lookup to determine whether the VID is valid ...
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... DSCP register to determine priority. Rate Limiting Support The KSZ8842M supports hardware rate limiting from 64 Kbps to 88 Mbps, independently on the “receive side” and on the “transmit side” per port basis. For 10-base T, a rate setting above 10 Mbps means the rate is not limited. On the receive side, the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control Registers ...
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... The KSZ8842M operates only as a managed switch. EEPROM Interface It is optional in the KSZ8842M to use an external EEPROM. In the case that an EEPROM is not used, the EEEN pin must be tied Low or floating. The external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information such as the host MAC address, base address, and default configuration settings ...
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... Figure 14. Near-end (Remote) Loopback Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2 of the KSZ8842M. The loopback path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’ ...
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... KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
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... Micrel Confidential CPU Interface I/O Registers The KSZ8842M provides an EISA-like, ISA-like, or VLBUS-like bus interface for the CPU to access its internal I/O registers. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is used for configuring operational settings, reading or writing control, status information, and transferring packets by reading and writing through the packet data registers ...
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... Address High Info [7:0] [7:0] Reserved Host MAC Memory BIST Address High Info [15:8] [15:8] Global Reset [7:0] Reserved Reserved Global Reset [15:8] Bus Configuration [7:0] Reserved Reserved Bus Configuration [15:8] Reserved Reserved Bank Select [7:0] Bank Select [15:8] 46 KSZ8842-16/32 MQL/MVL Bank 4 Bank 5 Bank 6 Reserved Reserved Reserved Reserved Reserved Rev. 1.4 Bank 7 ...
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... To 0xB 0xA 0xA - 0xB 0xB 0xC 0xC - 0xD 0xD 0xC To 0xF 0xE 0xE - 0xF 0xF November 2005 Bank Location Bank 9 Bank 10 Bank 11 Bank 12 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bank Select [7:0] Bank Select [15:8] 47 KSZ8842-16/32 MQL/MVL Bank 13 Bank 14 Bank 15 Rev. 1.4 ...
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... RX Frame Receive Byte Multicast Data Pointer Counter Table 3 [15:8] [15:8] [15:8] QMU Data Low [7:0] Reserved Reserved QMU Data Low [15:8] QMU Data High [7:0] QMU Data High [15:8] Reserved Bank Select [7:0] Bank Select [15:8] 48 KSZ8842-16/32 MQL/MVL Bank 20 Bank 21 Bank 22 Reserved Reserved Reserved Reserved Reserved Reserved Bank 23 Rev. 1.4 ...
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... To 0xB 0xA 0xA - 0xB 0xB 0xC 0xC - 0xD 0xD 0xC To 0xF 0xE 0xE - 0xF 0xF November 2005 Bank Location Bank 25 Bank 26 Bank 27 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bank Select [7:0] Bank Select [15:8] 49 KSZ8842-16/32 MQL/MVL Bank 28 Bank 29 Bank 30 Bank 31 Rev. 1.4 ...
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... Bank Location Bank 33 Bank 34 Bank 35 Switch Global Control 6 [7:0] Switch Global Control 6 [15:8] Switch Global Control 7 [7:0] Switch Global Control 7 [15:8] Reserved Reserved Bank Select [7:0] Bank Select [15:8] 50 KSZ8842-16/32 MQL/MVL Bank 36 Bank 37 Bank 38 MAC Address 1 [7:0] Reserved MAC Address 1 [15:8] MAC Address 2 [7:0] Reserved MAC Address 2 [15:8] MAC Address 3 [7:0] ...
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... Analog Test Access Data 5 Control 2 [7:0] [7:0] Reserved Reserved Indirect Analog Test Access Data 5 Control 2 [15:8] [15:8] Reserved Bank Select [7:0] Bank Select [15:8] 51 KSZ8842-16/32 MQL/MVL Bank 44 Bank 45 Bank 46 PHY1 MII- PHY2 MII- PHY1 LinkMD Control/Status Register Register Basic Control Basic Control [7:0] [7:0] [7:0] PHY1 MII- PHY2 MII- PHY1 LinkMD ...
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... Port2 Egress Host Rate Control Egress Rate Control [7:0] [7:0] Reserved Reserved Port2 Egress Host Rate Control Egress Rate Control [15:8] [15:8] Reserved Bank Select [7:0] Bank Select [15:8] 52 KSZ8842-16/32 MQL/MVL Bank 52 Bank 53 Bank 54 Reserved Reserved Port Reserved Port Reserved Port Reserved Port Port Reserved Port Bank 55 Rev. 1.4 ...
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... To 0xB 0xA 0xA - 0xB 0xB 0xC 0xC - 0xD 0xD 0xC To 0xF 0xE 0xE - 0xF 0xF November 2005 Bank Location Bank 57 Bank 58 Bank 59 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bank Select [7:0] Bank Select [15:8] 53 KSZ8842-16/32 MQL/MVL Bank 60 Bank 61 Bank 62 Bank 63 Rev. 1.4 ...
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... Description 15-8 0x03 if EEEN RW BARH Base Address High is Low or, the These bits are compared against the address on the bus ADDR[15:8] to determine the value from BASE for the KSZ8842M registers. EEPROM if EEEN is High 7-5 0x0 if EEEN is RW BARL Base Address Low Low or, the These bits are compared against the address on the bus ADDR[7:5] to determine the value from BASE for the KSZ8842M registers ...
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... MARM[15:0] = EEPROM 0x2(MAC Byte 4 and 3) MARH[15:0] = EEPROM 0x3(MAC Byte 6 and 5) The Host MAC address is used to define the individual destination address that the KSZ8842M responds to when receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are received from left to right, and the bits within each byte are received from right to left (LSB to MSB). For example, the actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101 ...
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... Bank 3 On-Chip Bus Control Register (0x00): OBCR This register controls the on-chip bus speed for the KSZ8842M used for power management when the external host CPU is running at a slow frequency. The default of the on-chip bus speed is 125 MHz without EEPROM. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best performance ...
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... EEPROM is used in the design (EEPROM Enable pin to High), the chip Base Address and host MAC address are loaded from the EEPROM immediately after reset. The KSZ8842M allows the software to access (read and write) the EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the EEPROM Software Access bit is set ...
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... Note: the SGCR3[5] in Bank 32 also needs to be enabled. 2 0x0 RW TXPE Transmit Padding Enable When this bit is set, the KSZ8842M automatically adds a padding field to a packet shorter than 64 bytes. Note: Setting this bit requires enabling the ADD CRC feature to avoid CRC errors for the transmit packet. 1 ...
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... RW RXFCE Receive Flow Control Enable When this bit is set, the KSZ8842M will acknowledge a PAUSE frame from the receive interface; i.e., the outgoing packets are pending in the transmit buffer until the PAUSE frame control timer expires. When this bit is cleared, flow control is not enabled. ...
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... When this bit is reset, the TX frame data pointer is manually controlled by user to access the TX frame location. 13- Reserved 10-0 0x0 RW TXFP TX Frame Pointer TX Frame Pointer index to the Frame Data register for access. This field reset to next available TX frame location when the TX Frame Data has been November 2005 KSZ8842-16/32 MQL/MVL 60 Rev. 1.4 ...
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... This register is mapped into two uni-directional buffers for 16-bit buses, and one uni- directional buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow moving words to and from the KSZ8842M regardless of whether the pointer is even, odd, or Dword aligned. Byte, word, and Dword access can be mixed on the fly in any order ...
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... When this bit is reset, the Receive Process Stopped interrupt is disabled. RXEFIE Receive Error Frame Interrupt Enable 7 0x0 RW When this bit is set, the Receive error frame interrupt is enabled. When this bit is reset, the Receive error frame interrupt is disabled. 6 Reserved November 2005 KSZ8842-16/32 MQL/MVL 62 Rev. 1.4 ...
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... This edge-triggered interrupt status is cleared by writing 1 to this bit. 7 0x0 RO RXEFIE Receive Error Frame Interrupt Status (W1C) When this bit is set, it indicates that the Receive error frame status has occurred. This edge-triggered interrupt status is cleared by writing 1 to this bit. 6 Reserved November 2005 KSZ8842-16/32 MQL/MVL 63 Rev. 1.4 ...
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... Bank 18 Receive Byte Counter Register (0x06): RXBC This register indicates the status of the current received frame and mirrors the Receive Byte Count word of the Receive Frame in the RXQ. Bit Default Value R/W Description 15- Reserved 10 RXBC Receive Byte Count Receive Byte Count. November 2005 KSZ8842-16/32 MQL/MVL 64 Rev. 1.4 ...
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... When the appropriate bit is cleared, the packet will drop. Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all multicast addresses are received regardless of the multicast table value. Banks 20 – 31: Reserved Except Bank Select Register (0xE). November 2005 KSZ8842-16/32 MQL/MVL 65 Rev. 1.4 ...
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... Bit Default R/W Description 15-8 0x88 RO Family ID Chip family ID 7-4 0x0 RO Chip ID 0x0 is assigned to KSZ8842M Revision ID 3-1 0x0 RO Start Switch start the chip switch is disabled. Bank 32 Switch Global Control Register 1 (0x02): SGCR1 This register contains the global control for the switch function. Bit ...
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... This may not be “fair” to the flow control port Excessive Collision Drop November 2005 KSZ8842-16/32 MQL/MVL 67 Rev. 1.4 ...
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... The switch supports only half duplex , 100BT in repeater mode Switch Host Half-Duplex Mode The KSZ8842M supports only half-duplex 100-BaseT throughput in repeater mode enable host port interface half-duplex mode, this bit must be set for repeater mode 0 = enable host port interface full-duplex mode.. Switch Flow Control Enable 5 ...
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... PnLED0 SPEED FULL_DPX [LEDSEL1, LEDSEL0] [1, 0] [1, 1] PnLED3 ACT ------ PnLED2 LINK ------ PnLED1 FULL_DPX/COL ------ PnLED0 SPEED ------ [LEDSEL1, LEDSEL0] [0, 0] P1LED3; P2LED3 RPT_COL; RPT_ACT P1LED2; P2LED2 RPT_LINK3/RX; RPT_ERR3 P1LED1; P2LED1 RPT_LINK2/RX; RPT_ERR2 P1LED0; P2LED0 RPT_LINK1/RX; RPT_ERR1 69 KSZ8842-16/32 MQL/MVL [0, 1] [1, 0] [1, 1] ------ ------ ------ ------ Rev. 1.4 ...
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... Unknown Packet Default Port(s) Specify which ports to send packets with unknown destination addresses. Feature is enabled by bit [7]. Bit 2 for the host port, bit 1 for port 2, and bit 0 for port 1 Banks 34 – 38: Reserved Except Bank Select Register (0xE) November 2005 KSZ8842-16/32 MQL/MVL 70 Rev. 1.4 ...
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... TOS/DiffServ/Traffic Class value is 0x08. 3-2 0 R/W DSCP[3:2] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x04. 1-0 0 R/W DSCP[1:0] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x00. November 2005 KSZ8842-16/32 MQL/MVL 71 Rev. 1.4 ...
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... TOS/DiffServ/Traffic Class value is 0x48. 3-2 0 R/W DSCP[35:34] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x44. 1-0 0 R/W DSCP[33:32] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x40. November 2005 KSZ8842-16/32 MQL/MVL 72 Rev. 1.4 ...
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... TOS/DiffServ/Traffic Class value is 0x88. 3-2 0 R/W DSCP[67:66] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x84. DSCP[65:64] 1-0 0 R/W The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x80. November 2005 KSZ8842-16/32 MQL/MVL 73 Rev. 1.4 ...
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... TOS/DiffServ/Traffic Class value is 0xc8. 3-2 0 R/W DSCP[99:98] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0xc4. DSCP[97:96] 1-0 0 R/W The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0xc0. November 2005 KSZ8842-16/32 MQL/MVL 74 Rev. 1.4 ...
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... Bank 42 Indirect Access Data Register 1 (0x02): IADR1 This register contains the indirect data for the switch function. Bit Default R/W Description 15-8 0x00 RO Reserved CPU Read Status Only for dynamic and statistics counter reads read is still in progress read has completed. November 2005 KSZ8842-16/32 MQL/MVL 75 Rev. 1.4 ...
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... This register contains the user defined register for the switch function. Bit Default R/W Description 15-3 0x0000 RO Reserved 2-0 0x0 RO Reserved Bank 44 Analog Testing Status Register (0x02): ATSR This register contains the user defined register for the switch function. Bit Default R/W Description 15-8 0x00 RO Reserved 7-0 0x00 RO Reserved November 2005 KSZ8842-16/32 MQL/MVL 76 Rev. 1.4 ...
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... Restart restart auto-negotiation normal operation. November 2005 Start: RXP2/RXM2 (port 2) Loop back: PMD/PMA of port 1’s PHY End: TXP2/TXM2 (port 2) 77 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 49 0x02 bit 8 Bank 49 0x02 bit 6 Bank 49 0x02 bit 7 Bank 49 0x02 bit 11 Bank 49 0x02 bit 13 Rev. 1.4 ...
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... RO Preamble Suppressed Not supported Complete 1 = auto-negotiation complete. November 2005 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 49 0x02 bit 5 Bank 49 0x04 bit 15 Bank 49 0x02 bit 9 Bank 49 0x02 bit 10 Bank 49 0x02 bit 12 Bank 49 0x02 bit 14 Bank 49 0x02 bit 15 Bit is same as: Bank 49 0x04 bit 6 78 Rev ...
Page 79
... RW Adv 100 Half 1= advertise 100 half-duplex capable not advertise 100 half-duplex capability. November 2005 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 49 0x04 bit 8 Bank49 0x04 bit 5 Bit is same as: Bank 49 0x02 bit 4 Bank49 0x02 bit 3 Bank49 0x02 bit 2 79 Rev ...
Page 80
... RW Force 100 November 2005 Start: RXP1/RXM1 (port 1) Loop back: PMD/PMA of port 2’s PHY End: TXP1/TXM1 (port 1) 80 KSZ8842-16/32 MQL/MVL Bank49 0x02 bit 1 Bank49 0x02 bit 0 Bit is same as: Bank 49 0x04 bit 4 Bank 49 0x04 bit 3 Bank 49 0x04 bit 2 Bank 49 0x04 bit 1 Bank 49 0x04 bit 0 ...
Page 81
... RO T4 Capable 0 = not 100 BASE-T4 capable 100 Full Capable November 2005 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 51 0x02 bit 7 Bank 51 0x02 bit 11 Bank 51 0x02 bit 13 Bank 51 0x02 bit 5 Bank 51 0x04 bit 15 Bank 51 0x02 bit 9 Bank 51 0x02 bit 10 Bank 51 0x02 bit 12 ...
Page 82
... Bank 46 PHY 2 PHYID High Register (0x06): PHY2IHR This register contains the PHY ID (high) for the switch port 2 function. Bit Default R/W Description 15-0 0x0022 RO PHYID High High order PHYID bits. November 2005 KSZ8842-16/32 MQL/MVL Bank 51 0x04 bit 6 Bank 51 0x04 bit 8 Bank 51 0x04 bit 5 82 Rev. 1.4 ...
Page 83
... Pause Link partner pause capability Reserved Adv 100 Full November 2005 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 51 0x02 bit 4 Bank 51 0x02 bit 3 Bank 51 0x02 bit 2 Bank 51 0x02 bit 1 Bank 51 0x02 bit 0 Bit is same as: Bank 51 0x04 bit 4 Bank 51 0x04 bit 3 83 ...
Page 84
... RW Power Saving (pwrsave disable power saving enable power saving. November 2005 KSZ8842-16/32 MQL/MVL Bank 51 0x04 bit 2 Bank 51 0x04 bit 1 Bank 51 0x04 bit 0 Bit is same as: Bank 49 0x00 bit 12 Bank 49 0x00 bit 14-13 Bank 49 0x00 bit 15 Bank 49 0x00 bit 8-0 ...
Page 85
... RW Remote (Near-End) Loopback (rlb perform remote loopback at Port 2's PHY(RXP2/RXM2 -> TXP2/TXM2. see November 2005 KSZ8842-16/32 MQL/MVL Bank 49 0x00 bit 9 Bit is same as: Bank 51 0x00 bit 12 Bank 51 0x00 bit 14-13 Bank 51 0x00 bit 15 Bank 51 0x00 bit 8-0 Bit is same as: Bank 51 0x04 bit 13 ...
Page 86
... RW TX Multiple Queues Select Enable 1 = the port output queue is split into four priority queues single output queue on the port. There is no priority differentiation even though packets are classified into high or low priority. November 2005 KSZ8842-16/32 MQL/MVL 86 Rev. 1.4 ...
Page 87
... Define the port’s Port VLAN membership. Bit 2 stands for the host port, bit 1 for port 2, and bit 0 for port 1. The port can only communicate within the membership. A ‘1’ includes a port in the membership; a ‘0’ excludes a port from the membership. November 2005 KSZ8842-16/32 MQL/MVL 87 Rev. 1.4 ...
Page 88
... Ingress and Egress rate limiting calculations. 0= IFG bytes are not counted Count Preamble Count preamble Bytes each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations preamble bytes are not counted. November 2005 KSZ8842-16/32 MQL/MVL 88 Rev. 1.4 ...
Page 89
... Mbps 1101 = 72Mbps 1110 = 80Mbps 1111 = 88Mbps Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (not limited). November 2005 KSZ8842-16/32 MQL/MVL 89 Rev. 1.4 ...
Page 90
... Mbps 1101 = 72Mbps 1110 = 80Mbps 1111 = 88Mbps Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (not limited). November 2005 KSZ8842-16/32 MQL/MVL 90 Rev. 1.4 ...
Page 91
... Notes: For 10BT, rate settings above 10Mbps are set to the default value 0000 (not limited). When multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. November 2005 KSZ8842-16/32 MQL/MVL 91 Rev. 1.4 ...
Page 92
... Notes: For 10BT, rate settings above 10Mbps are set to the default value 0000 (not limited). When multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. November 2005 KSZ8842-16/32 MQL/MVL 92 Rev. 1.4 ...
Page 93
... PHY (RXP1/RXM1 -> TXP1/TXM1, see Figure 15 normal operation Vct_fault_count VCT fault count. Distance to the fault. It’s approximately 0.4m*vct_fault_count. 93 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 47 0x00 bit 12 Bank 47 0x00 bit 14-13 Bank 47 0x00 bit 15 Bank 47 0x02 bit 3 Bank 47 0x02 bit 2 Bank 47 0x02 bit 1 Bank 47 0x00 bit 8-0 ...
Page 94
... Force Duplex 1 = force full duplex if ( disabled or ( enabled but failed force half duplex if ( disabled or ( enabled but failed. November 2005 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 45 0x00 bit 0 Bank 45 0x00 bit1 Bank 45 0x00 bit 9 Bank 45 0x00 bit 2 ...
Page 95
... Operation Duplex 1 = link duplex is full link duplex is half Far-End-Fault 1 = far-end-fault status detected. November 2005 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 45 0x08 bit 10 Bank 45 0x08 bit 8 Bank 45 0x08 bit 7 Bank 45 0x08 bit 6 Bank 45 0x08 bit 5 Bit is same as: Bank 45 0x00 bit 5 Bank 47 0x02 bit 5 ...
Page 96
... This register contains per port ingress rate control. See description in P1IRCR, Bank 48 (0x08) Bank 50 Port 2 Egress Rate Control Register (0x0A): P2ERCR This register contains per port egress rate control. See description in P1ERCR, Bank 48 (0x0A) November 2005 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 47 0x02 bit 4 Bank 45 0x02 bit 5 ...
Page 97
... PHY (RXP2/RXM2 -> TXP2/TXM2, see Figure 15 normal operation Vct_fault_count VCT fault count. The distance to the fault is approximately 0.4m*vct_fault_count. 97 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 47 0x04 bit 12 Bank 47 0x04 bit 14-13 Bank 47 0x04 bit 15 Bank 47 0x06 bit 3 Bank 47 0x06 bit 2 Bank 47 0x06 bit 1 Bank 47 0x04 bit 8-0 ...
Page 98
... RW Force Duplex 1 = force full duplex if ( disabled or ( enabled but failed force half duplex if ( disabled or (2) AN November 2005 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 46 0x00 bit 0 Bank 46 0x00 bit 1 Bank 46 0x00 bit 9 Bank 46 0x00 bit 2 Bank 46 0x00 bit 11 ...
Page 99
... RO Operation Duplex 1 = link duplex is full link duplex is half Far-End-Fault November 2005 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 46 0x08 bit 10 Bank 46 0x08 bit 8 Bank 46 0x08 bit 7 Bank 46 0x08 bit 6 Bank 46 0x08 bit 5 Bit is same as: Bank 46 0x00 bit 5 Bank 47 0x06 bit 5 Bank 46 0x02 bit 4 99 Rev ...
Page 100
... VID does not match the ingress port default VID packets are discarded. Reserved Reserved Transmit Enable 100 KSZ8842-16/32 MQL/MVL Bit is same as: Bank 47 0x06 bit 4 Bank 46 0x02 bit 5 Bank 46 0x02 bit 2 Bank 46 0x0A bit 10 Bank 46 0x0A bit 8 ...
Page 101
... Define the port’s Port VLAN membership. Bit 2 stands for host port, bit 1 for port 2, and bit 0 for port 1. The port can only communicate within the membership. A ‘1’ includes a port in the membership; a ‘0’ excludes a port from the membership. 101 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
Page 102
... MIB (Management Information Base) Counters The KSZ8842M provides 34 MIB counters for each port. These counters are used to monitor the port activity for network management. The MIB counters are formatted “per port” as shown in Table 14 and “all ports dropped packet” as shown in Table 16 ...
Page 103
... Successfully Tx frames on a port for which Tx is inhibited by more than one collision Description Reserved Counter Value Description TX packets dropped due to lack of resources TX packets dropped due to lack of resources RX packets dropped due to lack of resources RX packets dropped due to lack of resources 103 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
Page 104
... All Ports Dropped Packet MIB counters are not cleared after they are accessed. The application needs to keep track of overflow and valid conditions on these counters. November 2005 KSZ8842-16/32 MQL/MVL // If bit restart (reread) from this register // If bit restart (reread) from this register 104 Rev ...
Page 105
... The static DA look up result takes precedence over the dynamic DA look up result. If there match in both tables, the result from the static table is used. These entries in the static table will not be aged out by the KSZ8842M. Bit ...
Page 106
... Specifies the 2-bit counter for internal aging. Source port Identifies the source port where FID+MAC is learned: 00: port 1 01: port 2 10: port 3 FID Specifies the filter ID. MAC Address Specifies the 48-bit MAC address. Table 19. Dynamic MAC Address Table Format 106 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
Page 107
... R/W Specifies the IEEE 802.1Q 12 bits VLAN ID. If 802.1Q VLAN mode is enabled, KSZ8842M will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, the VID in the tag will be used. The look up process will start from the VLAN table look up. If the VID is not valid, the packet will be dropped and no address learning will take place ...
Page 108
... No (HS) heat spreader in this package. November 2005 (1) Pins Value VDDATX, VDDARX, VDDIO –0.5V to 4.0V All Inputs –0. All Outputs –0.5V to 4.0V N/A — N/A –55°C to 150°C Table 21. Maximum Ratings Min 3.1V 3.1V 0°C Table 22. Operating Ratings 108 KSZ8842-16/32 MQL/MVL Typ Max 3.3V 3.5V 3.3V 3.5V 70°C 125°C 32qC/W Rev. 1.4 ...
Page 109
... set Peak to peak 5MHz square wave 100: termination on the differential o output Peak to peak Table 23. Electrical Characteristics 109 KSZ8842-16/32 MQL/MVL Min Typ Max 122mA 90mA 2.0V 0.8V -10µA 10µA 2.4V 0.4V 10µA +0.95V +1.05V 2% 3ns 5ns 0ns 0.5ns + 0 ...
Page 110
... ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the RDN/WRN low until the ARDY returns to high. Table 24. Asynchronous Cycle (ADSN = 0) Timing Parameters November 2005 valid valid t7 t9 Figure 16. Asynchronous Cycle – ADSN = 0 Min 110 KSZ8842-16/32 MQL/MVL t2 t4 valid t6 t8 t10 Typ Max Unit ...
Page 111
... ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the RDN/WRN low until the ARDY returns to high. Table 25. Asynchronous Cycle using ADSN Timing Parameters November 2005 t8 valid t6 valid t1 t4 valid t7 t2 t10 Figure 17. Asynchronous Cycle – Using ADSN Min 111 KSZ8842-16/32 MQL/MVL t11 Typ Max Unit ...
Page 112
... ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the RDN/WRN low until the ARDY returns to high. Table 26. Asynchronous Cycle using DATACSN Timing Parameters November 2005 t1 t5 valid Min 112 KSZ8842-16/32 MQL/MVL t2 valid t10 Typ Max Unit ...
Page 113
... A1-A15, AEN, BExN[3:0] setup to ADSN t2 A1-A15, AEN, BExN[3:0] hold after ADSN rising t3 A4-A15, AEN to LDEVN delay November 2005 Figure 19. Address Latching Cycle for All Modes Min Table 27. Address Latching Timing Parameters 113 KSZ8842-16/32 MQL/MVL Typ Max Unit Rev. 1.4 ...
Page 114
... SRDYN hold to BCLK rising t10 DATACSN hold to BCLK rising t11 SWR hold to BCLK falling t12 CYCLEN hold to BCLK rising Table 28. Synchronous Burst Write Timing Parameters November 2005 Figure 20. Synchronous Burst Write Cycles – VLBUSN = 1 114 KSZ8842-16/32 MQL/MVL Min Typ Max Unit ...
Page 115
... CYCLEN hold to BCLK rising Table 29. Synchronous Burst Read Timing Parameters November 2005 t5 t4 data0 data1 Min Typ 115 KSZ8842-16/32 MQL/MVL t10 t11 t12 data2 data3 Max Unit Rev. 1.4 ...
Page 116
... RDYRTNN setup to BCLK t12 RDYRTNN hold to BCLK Table 30. Synchronous Write (VLBUSN = 0) Timing Parameters November 2005 t2 valid valid t9 t10 t11 t12 Min Typ 116 KSZ8842-16/32 MQL/MVL Max Unit Rev. 1.4 ...
Page 117
... RDYRTNN setup to LCLK rising t11 RDYRTNN hold after LCLK rising Table 31. Synchronous Read (VLBUSN = 0) Timing Parameters November 2005 t2 valid valid t8 t9 t10 t11 Min Typ 117 KSZ8842-16/32 MQL/MVL Max Unit Rev. 1.4 ...
Page 118
... Start bit Figure 24. EEPROM Read Cycle Timing Diagram Timing Description Parameter tcyc Clock cycle ts Setup time th Hold time November 2005 tcyc D15 D14 Min Typ Table 32. EEPROM Timing Parameters 118 KSZ8842-16/32 MQL/MVL D0 D1 D13 Max Unit Rev. 1.4 ...
Page 119
... Clock pulse to CTD data pulse t Clock pulse to CTC clock pulse Number of Clock/Data pulses per burst November 2005 Figure 25. Auto-Negotiation Timing Min Typ 100 55.5 64 111 128 17 Table 33. Auto Negotiation Timing Parameters 119 KSZ8842-16/32 MQL/MVL Max Unit 69.5 µs 139 µs 33 Rev. 1.4 ...
Page 120
... Micrel Confidential Reset Timing As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing requirement for the KSZ8842M supply voltage (3.3V). The reset timing requirement is summarized in the Figure 26 and Table 34. Figure 26. Reset Timing Symbol Parameter sr Stable supply voltages to reset High ...
Page 121
... Yes S558-5999-U7 Yes LF8505 Yes LF-H41S Yes Table 36. Qualified Single Port Magnetic Value 25 r50 20 25 Table 37. Typical Reference Crystal Characteristics 121 KSZ8842-16/32 MQL/MVL Test Condition 100mV, 100kHz, 8mA 1MHz (min) 0MHz – 65MHz Number of Port Units MHz ppm ...
Page 122
... Micrel Confidential Package Information November 2005 Figure 27. 128-Pin PQFP Package 122 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
Page 123
... Micrel Confidential November 2005 Figure 28. Optional 128-Pin LQFP Package 123 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
Page 124
... A packet larger than the standard Ethernet packet (1500 bytes). Large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc. An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, 124 KSZ8842-16/32 MQL/MVL . CRC for Rev. 1.4 ...
Page 125
... Commonly a cable containing 4 twisted pairs of wires. The wires are twisted in such a manner as to cancel electrical interference generated in each wire, therefore shielding is not required. A configuration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. 125 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...
Page 126
... Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify November 2005 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. 126 KSZ8842-16/32 MQL/MVL Rev. 1.4 ...