M66591GP Renesas Electronics Corporation., M66591GP Datasheet
M66591GP
Available stocks
Related parts for M66591GP
M66591GP Summary of contents
Page 1
... M66591GP ASSP (USB2.0 Peripheral Controller) Overview 1 1.1 Overview The M66591 is a general-purpose USB (Universal Serial Bus) device controller compliant with the Universal Serial Bus Specification Revision 2.0 and supports both Hi-Speed and Full-Speed transfer. The USB Hi-Speed and Full-Speed transceiver are built-in, and the M66591 meets control, bulk and interrupt transfer types which are defined in the Universal Serial Bus Specification Revision 2 ...
Page 2
... VDD 73 DGND(GND) 74 DREQ 75 DACK 76 DSTB_N 77 DEND 78 RST_N 79 VIF 80 M66591GP: 80pin LQFP (0.4mm pitch, Outline: 80P6R- M66591GP (Top View) Figure 1.1 Pin Configuration of M66591 40 D0 A7/ALE ...
Page 3
The pin functions of the M66591 are shown in Table 1.1. Item Pin Name Input/Output CPU D15-D8 Input/Output interface D7/AD7-D1/AD Input/Output 1, D0 A7/ALE, A6-A1 Input CS_N Input RD_N Input WR1_N Input ...
Page 4
Item Pin Name Input/Output RPU Input TR_ON Output VBUS Input REFRIN Input USB status CONF_ON Output output SUSP_ON Output Clock XIN Input XOUT Output System RST_N Input control TEST1-0 Input Power AFEAVDD ...
Page 5
1.4 Pin Functions The pin functions of the M66591are shown in Figure 1.2. DMA Interface D7/AD7-D1/AD1, D0 CPU SD7/PA7-SD0/PA0 Interface A7/ALE, A6-A1 System Control ...
Page 6
1.5 Block Diagram M66591 contains four blocks, SIE (Serial Interface Engine) side block and CPU side block and bus interface unit (BIU) and FIFO memory. SIE side block includes USB transceiver (UTM), ...
Page 7
Registers 2 Bit Numbers: Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the registers located at odd addresses are b15-b8, and those at even ...
Page 8
2.1 Register Mapping M66591 register mapping is shown in Figure 2.1, Figure 2.2 and Figure 2.3, each register is described below. +1 address Address b15 H’00 USB Transceiver Control Register 0 H’02 ...
Page 9
Address +1 address b15 H’48 INT Pin Configuration Register 3 H’4A H’4C INT Pin Configuration Register 4 H’4E H’50 H’52 H’54 H’56 H’58 H’5A H’5C H’5E H’60 H’62 H’64 H’66 H’68 H’6A ...
Page 10
Address +1 address b15 H’9A H’9C H’9E H’A0 H’A2 H’A4 H’A6 H’A8 H’AA Note: Refer to each register described below ...
Page 11
2.2 Register Bit Map Odd number address (001h USB Transceiver Control Register 0 (USBTrnsCtrl0 XTAL [1:0] XCKE RCKE PLLC SCKE USB Transceiver Control Register 1 (USBTrnsCtrl1) ...
Page 12
Odd number address (001h D0_FIFO Port Control Register 0 (D0_FIFOPortCtrl0 RCNT REW ABCR 3 2 D0_FIFO Port Control Register 2 (D0_FIFOPortCtrl2 BVAL BCLR FRDY ...
Page 13
Odd number address (001h Interrupt Status Register 3 (INTStatus3 USB Address Register (USBAddress USB Request Register ...
Page 14
2.3 USB Transceiver Control Register 0 USB Transceiver Control Register 0 (USBTrnsCtrl0) B15 Xtal [1:0] XCKE RCKE ...
Page 15
(6) HSE (Hi-Speed Enable) Bit (b7) This bit sets enable/disable of the Hi-Speed mode. When the Hi-Speed mode is disabled, M66591 is used as the Full-Speed only device. When the Hi-Speed mode ...
Page 16
2.4 USB Transceiver Control Register 1 USB Transceiver Control Register 1 (USBTrnsCtrl1) b15 Bit name 15~7 ...
Page 17
2.5 HS/FS Mode Register HS/FS Mode Register (HSFSMode) b15 Bit name 15~9 Reserved. Set it to ...
Page 18
2.6 Test Mode Register Test Register (TestMd) b15 SUSPEN CONFEN Bit name 15 SUSPEN SUSP_ON Pin ...
Page 19
2.7 Data Pin & FIFO/DMA Control Pin Configuration Register 0 Data Pin & FIFO/DMA Control Pin Configuration Register 0 (PinCtrlCfg0) b15 ...
Page 20
2.8 Data Pin & FIFO/DMA Control Pin Configuration Register 1 Data Pin & FIFO/DMA Control Pin Configuration Register 1 (PinCtrlCfg1) b15 LDRV ...
Page 21
2.9 Data Pin & FIFO/DMA Control Pin Configuration Register 2 Data Pin & FIFO/DMA Control Pin Configuration Register 2 (PinCtrlCfg2) b15 DreqA Burst DreqE ...
Page 22
(5) RWstb (RD/WR Strobe Mode) Bit (b9) This bit selects the read/write strobe signal for DMA data transfer. Set this bit to “1” in order to use DMA transfer in split bus ...
Page 23
2.10 C_FIFO Port Register 0 C_FIFO Port Register 0 (C_FIFOPort0) b15 Bit name 15~0 C_FIFO_Port [15:0] ...
Page 24
2.11 D0_FIFO Port Register 0 D0_FIFO Port Register 0 (D0_FIFOPort0) b15 Bit name 15~0 D0_FIFO_Port [15:0] ...
Page 25
2.12 DCP Continuous Transmit Data Length Register DCP Continuous Transmit Data Length Register (DCPSdln) b15 Bit ...
Page 26
2.13 C_FIFO Port Control Register 0 C_FIFO Port Control Register 0 (C_FIFOPortCtrl0) b15 RCNT REW Bit ...
Page 27
(3) MBW (FIFO Access Maximum Bit Width) Bit (b10) This bit selects the bit width of the C_FIFO port access. 0: 8-bit width 1: 16-bit width When changing the MBW setting, the ...
Page 28
2.14 C_FIFO Port Control Register 1 C_FIFO Port Control Register 1 (C_FIFOPortCtrl1) b15 BVAL BCLR FRDY ...
Page 29
(2) When data have been written up to the MaxPacketSize in non-continuous transfer mode. When the buffer becomes empty, this bit is cleared. Writing “0” to this bit is invalid. Further, the ...
Page 30
2.15 C_FIFO Port Control Register 2 C_FIFO Port Control Register 2 (C_FIFOPortCtrl2) b15 TGL SCLR SBUSY ...
Page 31
2.16 D0_FIFO Port Control Register 0 D0_FIFO Port Control Register 0 (D0_FIFOPortCtrl0) b15 RCNT REW ABCR ...
Page 32
written to the REW bit concurrently with renewal of the Current_PIPE [2:0] bits, the rewind operation is executed to the FIFO buffer of the renewed PIPE. (3) ABCR (Automatic Buffer Clear Mode) ...
Page 33
(7) Current_PIPE [2:0] (D0_FIFO Port Access PIPE Designate) Bits (b2-b0) These bits designate the access PIPE to the D0_FIFO port. Do not change each configuration register (max. packet size, etc.) of the ...
Page 34
2.17 D0_FIFO Port Control Register 2 D0_FIFO Port Control Register 2 (D0_FIFOPortCtrl2) b15 BVAL BCLR FRDY ...
Page 35
the BCLR bit. This bit is changed from “0” to “1” on the following conditions: (1) When data have been written until the buffer becomes full in continuous transfer mode. (2) When ...
Page 36
2.18 D0_FIFO Port Control Register 3 D0_FIFO Port Control Register 3 (D0_FIFOPortCtrl3) b15 Bit name 15~0 ...
Page 37
2.19 INT Pin Configuration Register 0 INT Pin Configuration Register 0 (INTPinCfg0) b15 VBSE RSME DVSE ...
Page 38
(2) RSME (Resume Interrupt Enable) Bit (b14) This bit sets enable/disable of the resume interrupt. When this bit is set to “1”, the interrupt is occurs if the RESM bit is set ...
Page 39
(14) CMPL (Control Transfer Complete) Bit (b1) This bit selects whether to set the CTRT bit to “1” or not when the status stage completes during the control transfer. (15) SERR (Control ...
Page 40
2.20 INT Pin Configuration Register 1 INT Pin Configuration Register 1 (INTPinCfg1) b15 Bit name 15~2 ...
Page 41
2.21 INT Pin Configuration Register 2 INT Pin Configuration Register 2 (INTPinCfg2) b15 ...
Page 42
2.22 INT Pin Configuration Register 3 INT Pin Configuration Register 3 (INTPinCfg3) b15 ...
Page 43
2.23 INT Pin Configuration Register 4 INT Pin Configuration Register 4 (INTPinCfg4) b15 ...
Page 44
2.24 Interrupt Status Register 0 Interrupt Status Register 0 (INTStatus0) b15 VBUSINT RESM DVST CTRT Bit ...
Page 45
Bit name 7 VBUSSTS VBUS Level Port 6~4 DVSQ [2:0] Device State 3 VALID Setup Packet Detect 2~0 CTSQ [2:0] Control Transfer Stage Note optional value. (1) VBUSINT ...
Page 46
(4) CTRT (Control Transfer Stage Transition Interrupt) Bit (b11) This bit indicates the transition of stage in control transfers. The control transfer stage transition interrupt includes the following fifth factors: Setup stage ...
Page 47
(11) CTSQ [2:0] (Control Transfer Stage) Bits (b2-b0) These bits indicate the present stage in the control transfer. Note for clearing the VBUSINT/RESM/SOFR/DVST/CTST status bits: In order to continuously clear status bits ...
Page 48
2.25 Interrupt Status Register 1 Interrupt Status Register 1 (INTStatus1) b15 Bit ...
Page 49
(1) PIPEB_RDY6 (PIPE6 Buffer Ready Interrupt) Bits (b6) This bit indicates that PIPE6 buffer is kept in read ready state. This bit is cleared to “0” by writing “0”. This bit is ...
Page 50
2.26 Interrupt Status Register 2 Interrupt Status Register 2 (INTStatus2) b15 Bit ...
Page 51
(1) PIPEB_NRDY6 (PIPE6 Buffer Not Ready Interrupt) Bits (b6) This bit is set to “1” when IN token/OUT token is received with PIPE6 buffer at not ready state. The not ready status ...
Page 52
Note for clearing the buffer not ready interrupt (PIPEB_NRDY6-PIPEB_NRDY1/DCP_NRDY) status bits: In order to continuously clear status bits while the PIPEB_NRDY6-PIPEB_NRDY1/DCP_NRDY status bits are set to “1” by being multiplexed, the access ...
Page 53
2.27 Interrupt Status Register 3 Interrupt Status Register 3 (INTStatus3) b15 Bit name 15~7 Reserved. ...
Page 54
(1) PIPEB_EMP_OVR6 (PIPE6 Buffer Empty/Size-Error Interrupt) Bits (b6) This bit indicates that the received data size exceeds the maximum packet size or that the buffers of PIPE6 are empty. (1) When the ...
Page 55
(5) PIPEB_EMP_OVR2 (PIPE2 Buffer Empty/Size-Error Interrupt) Bits (b2) This bit indicates that the received data size exceeds the maximum packet size or that the buffers of PIPE2 are empty. (1) When the ...
Page 56
2.28 USB Address Register USB Address Register (USBAddress) b15 Bit name 15~7 Reserved. Set it to ...
Page 57
2.29 USB Request Register 0 USB Request Register 0 (USBReq0) b15 bRequest [7: Bit name 15~8 ...
Page 58
2.30 USB Request Register 1 USB Request Register 1 (USBReq1) b15 Bit name 15~0 wValue [15:0] ...
Page 59
2.31 USB Request Register 2 USB Request Register 2 (USBReq2) b15 Bit name 15~0 wIndex [15:0] ...
Page 60
2.32 USB Request Register 3 USB Request Register 2 (USBReq3) b15 Bit name 15~0 wLength [15:0] ...
Page 61
2.33 DCP Configuration Register 1 DCP Configuration Register 1 (DCPCfg1) b15 Bit name 15~9 Reserved. Set ...
Page 62
2.34 DCP Configuration Register 2 DCP Configuration Register 2 (DCPCfg2) b15 Bit name 15~7 Reserved. Set ...
Page 63
2.35 DCP Control Register DCP Control Register (DCPCtrl) b15 BSTS Bit name 15 BSTS Control PIPE ...
Page 64
(3) NYETMD (NYET Response Mode) Bit (b4) This bit sets the NYET response mode. 0: Automatic response mode (ACK/NYET is automatically selected.) 1: ACK response only mode (Always with ACK response. No ...
Page 65
2.36 PIPE Configuration Select Register PIPE Configuration Select Register (PipeCfgSel) b15 Bit name 15~3 Reserved. Set ...
Page 66
2.37 PIPE Configuration Window Register 0 PIPE Configuration Window Register 0 (PipeCfgWin0) b15 PEN ITMD Bit ...
Page 67
(2) ITMD (Interrupt Transfer Toggle Mode) Bit (b13) This bit sets the enable/disable of data resend function at interrupt transfer. This bit is valid only for PIPE5 and PIPE6. The written to ...
Page 68
The transmit completes under any one of the following conditions when setting the PIPE to IN: • Transmits the data equal to 512 bytes • Transmits the short packet or transmits the ...
Page 69
2.38 PIPE i Control Register (i=1~4) PIPE 1 Control Register (Pipe1Ctrl) PIPE 2 Control Register (Pipe2Ctrl) PIPE 3 Control Register (Pipe3Ctrl) PIPE 4 Control Register (Pipe4Ctrl) b15 BSTS 0 ...
Page 70
(3) SQCLR (Sequence Bit Clear) Bit (b8) This bit clears the sequence bit of the PIPE1 to PIPE4 to set the next data PID to the “DATA0”. The sequence bit is toggled ...
Page 71
2.39 PIPE i Control Register (i=5~6) PIPE 5 Control Register (Pipe5Ctrl) PIPE 6 Control Register (Pipe6Ctrl) b15 BSTS ...
Page 72
(4) PID [1:0] (Response PID) Bits (b1-b0) These bits set the PID for response of PIPE5 and PIPE6. 00: NAK response The NAK response is executed independent to buffer status. 01: BUF ...
Page 73
M66591 OPERATIONS 3 3.1 System Control 3.1.1 Clock M66591 is able to use the crystal oscillator or the external clock input. Oscillation factor is selected by the XTAL [1:0] bits of USB ...
Page 74
3.1.2 Reset M66591 has three types reset, hardware reset, software reset by register setting (USBE bit), and USB reset. The hardware reset will clear the value of all register. The software reset ...
Page 75
3.2 M66591 Initial Setting and Clock Control This chapter explains the method of initial setting, the detection method of attach/detach to the host, and the execution method of clock control and remote ...
Page 76
3.2.2 Process After Detection of Attach/Detach (VBUS Interrupt) M66591 uses VBUS interrupt to detect attach to the host to or detach from the host. The VBUS interrupt occurs when either “Low”->”High” or ...
Page 77
3.2.3 USB Attach Process AfterM66591 detects attach to the host, the USB attach processing is executed. The basic details of the USB attach processing are as follows: (1) Select M66591 operation mode: ...
Page 78
3.2.4 USB Detach Process After M66591 detects detach from the host, the USB detach processing is executed. The basic details of the USB detach processing are as follows: (1) Suspend of D+ ...
Page 79
3.2.5 Clock Control in Suspend/Resume M66591 clock must be controlled by the USB bus status in a system requiring low power consumption control. M66591 occurs the device state transition interrupt (DVST) after ...
Page 80
The flowchart of Figure 3.8 shows the clock control processing in suspend and in resume. Resume interrupt processing Waiting for oscillation stable Enabling RCLK operation (RCKE='1') Enabling PLL operation (PLLC='1') Waiting for ...
Page 81
3.2.6 Execution Method of Remote Wakeup Output The remote wakeup means that the remote wakeup signal is output and the suspended state is canceled when the USB bus is kept in suspended ...
Page 82
3.3 Interrupt 3.3.1 Features There are 7 factors of interrupts in M66591. The 7 factors of interrupts is shown in Table 3.2. The interrupt factors can set to enable/disable by the INT ...
Page 83
INT_N Edge/level Generator Circuit INT Pin Configuration Register 0 Bit Name Interrupt Status Register 0 Bit Name ...
Page 84
<Edge sense> Interrupt factor 1 Interrupt factor 2 Interrupt pin (Low active) <Level sense> Interrupt factor 1 Interrupt factor 2 Interrupt pin (High active) 3.3.2 VBUS (Detection of Attach to Host/Detach from ...
Page 85
USB bus reset detect (When URST bit ="1", DVST bit is set to "1") USB bus reset detect (When URST bit ="1", DVST bit is set to "1") SET_ADDRESS execute [Address = ...
Page 86
3.3.5 Control Transfer Stage Transition Interrupt The control transfer stage transition of M66591 is shown in Figure 3.13. Control transfer stage transition interrupt occurs when a stage transition occurs by the control ...
Page 87
3.3.6 PIPE Buffer Ready Interrupt The condition of M66591 INTR interrupt occurring is shown in Table 3.3. The timing of M66591 INTR interrupt occurring is shown in Figure 3.14. The status of ...
Page 88
3.3.7 PIPE Buffer Not Ready Interrupt The timing of M66591INTN interrupt occurring is shown in Figure 3.15. The condition of INTN interrupt occurring is described below. The status of each PIPE is ...
Page 89
3.4 Control Transfer and Enumeration The control transfer consists of the setup stage, data stage, and status stage. M66591 executes the stage control and notifies the CPU of the stage transition by ...
Page 90
3.4.5 Overview of Control Transfer Operation The overview of control transfer operation is shown in Figure 3.17 to Figure 3.22 USB bus SETUP ADDR EP CRC5 DATA0 8 bytes data (CW) ACK ...
Page 91
USB bus SETUP ADDR EP CRC5 DATA0 8 bytes data (CR) ACK IN ADDR EP CRC5 NAK CRC5 IN ADDR EP NAK IN ADDR EP CRC5 DATA1 MAX packet size data ACK ...
Page 92
USB bus SETUP ADDR EP CRC5 DATA0 8 bytes data (ND) ACK IN ADDR EP CRC5 NAK IN ADDR EP CRC5 NAK CRC5 IN ADDR EP NAK IN ADDR EP CRC5 NAK ...
Page 93
USB bus CRC5 SETUP ADDR EP DATA0 8 bytes data (CR) ACK IN ADDR EP CRC5 NAK CRC5 IN ADDR EP NAK OUT ADDR EP CRC5 DATA1 CRC16 STALL SETUP ADDR EP ...
Page 94
USB bus CRC5 SETUP ADDR EP DATA0 8 bytes data (CR) ACK CRC5 IN ADDR EP NAK SETUP ADDR EP CRC5 DATA0 8 bytes data (CR) ACK IN ADDR EP CRC5 NAK ...
Page 95
USB bus SETUP ADDR EP CRC5 DATA0 8 bytes data (CR) ACK IN ADDR EP CRC5 NAK IN ADDR EP CRC5 NAK IN ADDR EP CRC5 DATA1 MAX packet size data ACK ...
Page 96
3.5 PIPE and PIPE Control M66591 has 6PIPEs, PIPE1 to PIPE6, except for DCP. Each of these 6PIPEs (PIPE1 to PIPE6) can be set to bulk transfer and interrupt transfer. Table 3.4 ...
Page 97
3.5.4 Response PID The response PID is set via PID [1:0] bits of DCP Control Register (DCPCtrl) and PIPE i Control Register (i=1~6). In some case, PID [1:0] bits will be set ...
Page 98
3.5.7 Continuous Transfer Function The PIPE buffer can operate either in the continuous mode or the non-continuous mode by setting CNTMD bit of DCP Configuration Register 1 (DCPCfg1) and PIPE Configuration Window ...
Page 99
3.6 Buffer Memory 3.6.1 Buffer Memory Assignment and Buffer Area The buffer memory of DCP and PIPE1-PIPE6 is assigned to a fixed buffer memory area and size not necessary to ...
Page 100
3.6.2.1 FIFO Port Select The FIFO port access of each PIPE of M66591 is shown in Table 3.7. The PIPE accessed by C_FIFO Port Register or D0_FIFO Port Register can be selected ...
Page 101
3.6.2.4 Reading the buffer memory on the SIE side (CFIFO port reading direction) Even in the “FRDY=0” state, when data cannot be read from the buffer memory, confirming the SBUSY bit in ...
Page 102
The DTLN hold timing after FIFO read access The DTLN valid timing after FIFO read access Even in the time of FIFO accessing, there no CPU_DTLN [9:0] bits and DMA_DTLN [9:0] bits ...
Page 103
3.7.2 DMA transfer method The DMA transfer can be selected as the cycle steal mode or the burst transfer mode. It can be selected by the Burst bit of Data Pin & ...
Page 104
(2) Burst mode (Burst = “1”) At burst mode, the DREQ pin is asserted until all data transfers in the buffer are completed, and is negated when the transfer completes. (B-1) DMA ...
Page 105
3.7.3 DEND Pin M66591 is able to terminate DMA transfers that used the DEND pin. The DEND pin has separate input and output functions, depending on the USB data transfer direction. (1) ...
Page 106
3.7.5 Transaction counter (D0_FIFO port reading direction) The transaction counter is a function that operates when the pipe selected for the D0_FIFO port has been set in the direction of reading data ...
Page 107
Electrical characteristics 4 4.1 Absolute maximum ratings Symbol VDD Core supply voltage VIF IO supply voltage AFEAVDD USB transceiver block analog supply voltage AFEDVDD USB transceiver block digital supply voltage BIASVDD BIAS ...
Page 108
4.3 Electrical Characteristics (VIF = 2.7~3.6V, VDD = 3.0~3.6V) Symbol Parameter V High input voltage IH V Low input voltage IL V High input voltage IH V Low input voltage IL VT+ ...
Page 109
Symbol Parameter Icc(A) Average supply current at Hi-Speed operation Icc(S) Supply current in static mode C Pin density (Input Pin density OUT (Output, Input/Output) Note 1: A7-1, TEST0, TEST1, MPBUS ...
Page 110
4.4 Electrical Characteristics (VIF = 1.7~2.0V, VDD = 3.0~3.6V) Symbol Parameter V High input voltage IH V Low input voltage IL V High input voltage IH V Low input voltage IL Threshold ...
Page 111
Symbol Parameter Icc(A) Average supply current in operation mode ( in Hi-Speed ) Icc(S) Supply current in static mode C Pin density (Input Pin density OUT (Output, Input/Output) Note 1: ...
Page 112
4.5 Measurement circuit 4.5.1 Pins except for USB buffer block Input VDD Elements to P.G. be measured 50Ω C GND 4.5.2 USB buffer block (Full-Speed) VDD TR_ON R =1.5KΩ L RPU Elements ...
Page 113
4.6 Electrical characteristics (D+/D-) 4.6.1 DC characteristics Symbol Parameter Serial resistance between R s DFP (DFM) and DHP (DHF) R Output impedance pull-up resistance pu Input characteristics when set ...
Page 114
4.7 Switching Characteristics (VIF = 3.0~3.6V or 1.7~2.0V) Symbol ta (A) Address access time tv (A) Data valid time after address ta (CTRL - D) Data access time after control tv (CTRL ...
Page 115
4.8 Required Timing Conditions (VIF = 3.0~3.6V or 1.7~2.0V) Symbol tsuw (A) Address write setup time tsur (A) Address read setup time tsu (A - ALE) Address write setup time when multiplex ...
Page 116
4.9 Timing diagrams Table 4.1 and Table 4.2 shows index for register access and FIFO of M66591. Bus specification Separate bus Separate bus Multiplex bus Multiplex bus Bus specification Separate bus Separate ...
Page 117
4.9.1 CPU write timing (when set to separate bus) A7-1 CS_N Note 1-4 WR1_N, WR0_N Note 1-2 D15-0 4.9.2 CPU read timing (when set to separate bus) ta(A) 31 tsur(A) A7-1 CS_N ...
Page 118
4.9.3 CPU write timing (when set to multiplex bus) tsu (A - ALE) AD7-1 / D15-0 36 ALE CS_N Note 2-4 WR1_N, WR0_N Note 2-2 4.9.4 CPU read timing (when set to ...
Page 119
4.9.5 DMA transfer write timing (when set to separate bus and cycle steal transfer) DREQ Note 3-1 DACK Note 3-8 WR1_N, WR0_N Note 3-2 D15-0 DEND 4.9.6 DMA transfer read timing (when ...
Page 120
4.9.7 DMA transfer write timing (when set to split bus and cycle steal transfer) DREQ Note 3-1 DACK Note 3-8 DSTRB_N Note 3-4 SD7-0 DEND 4.9.8 DMA transfer read timing (when set ...
Page 121
4.9.9 DMA transfer read timing (when set to split bus and cycle steal transfer: Obus = 0) DREQ Note 3-1 DACK Note 3-8 DSTRB_N Note 3-4 td (DREQ - DV) SD7-0 Note ...
Page 122
4.9.11 DMA transfer read timing (when set to separate bus and cycle steal transfer) DREQ Note 3-1 A7-1 CS_N RD_N Note 3-6 D15-0 ta (CTRL - DendV) DEND Note 3-1: DACK=Low level ...
Page 123
4.9.12 DMA transfer write timing (when set to multiplex bus and cycle steal transfer) DREQ 32 tsu (A - ALE) AD7-1 / D15-0 36 ALE CS_N Note 4-3 WR1_N,WR0_N Note 4-1 DEND ...
Page 124
4.9.13 DMA transfer read timing (when set to multiplex bus and cycle steal transfer) DREQ A7-1 / D15-0 ALE CS_N Note 4-3 RD_N ta (CTRL - DendV) 11 Note 4-2 DEND Note ...
Page 125
4.9.14 DMA transfer write timing (when set to separate bus and burst transfer) DREQ DACK 48 WR0_N, WR1_N Note 5-1 D15-0 DEND 4.9.15 DMA transfer read timing (when set to separate bus ...
Page 126
4.9.16 DMA transfer write timing (when set to split bus and burst transfer) DREQ DACK 48 tw(CTRL_B) DSTRB_N Note 5-3 43 SD7-0 DEND 4.9.17 DMA transfer read timing (when set to split ...
Page 127
4.9.18 DMA transfer read timing (when set to split bus and burst transfer: Obus = 0) DREQ DACK 48 tw (CTRL_B) STRB_N Note 5-3 23 td(DREQ-DV) SD7-0 Note 5-6 24 td(DREQ-DendV) DEND ...
Page 128
4.9.20 DMA transfer read timing (when set to separate bus and burst transfer) DREQ 31 tsur (A) Address is A7-1 established CS_N 48 tw (CTRL_B) RD_N Note 5 ...
Page 129
4.9.21 DMA transfer write timing (when set to multiplex bus and burst transfer) DREQ 32 tsu (A - ALE) thw (A - ALE) AD7-1 / D15 (ALE) ALE CS_N Note ...
Page 130
4.9.22 DMA transfer read timing (when set to multiplex bus and burst transfer) DREQ 32 tsu(A-ALE) th(A-ALE) AD7-1 / D15-0 36 tw(ALE) ALE CS_N Note 6-3 RD_N Note 6-2 DEND Note 6-1: ...
Page 131
4.10 Interrupt Timing INT CS_N, WR0_N, WR1_N Note 7-1 Note 7-1: Writing through the combination of CS_N, WR0_N and WR1_N is carried out during the overlap of active (Low). The specification from ...
Page 132
REVISION HISTORY Rev. Date Page 1.00 Nov. 30, 2004 - Description First edition issued M66591 Data Sheet Summary ...
Page 133
Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...