PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


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PIC16F688
10.1.1.4
TSR Status
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
10.1.1.5
Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set the
EUSART will shift 9 bits out for each character transmit-
ted. The TX9D bit of the TXSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the 8 Least Significant bits into the TXREG. All nine bits
of data will be transferred to the TSR shift register
immediately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 10.1.2.7 “Address
Detection” for more information on the Address mode.
FIGURE 10-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC4/C2OUT/TX/CK
Start bit
pin
TXIF bit
(Transmit Buffer
1 T
CY
Reg. Empty Flag)
Word 1
TRMT bit
Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)
FIGURE 10-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
RC4/C2OUT/TX/CK
Start bit
pin
1 T
CY
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
Word 1
(Transmit Shift
Transmit Shift Reg.
Reg. Empty Flag)
Note:
This timing diagram shows two consecutive transmissions.
DS41203D-page 86
10.1.1.6
Asynchronous Transmission Set-up:
1.
Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 10.3 “EUSART Baud
Rate Generator (BRG)”).
2.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3.
If 9-bit transmission is desired, set the TX9 con-
trol bit. A set ninth data bit will indicate that the 8
Least Significant data bits are an address when
the receiver is set for address detection.
4.
Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
5.
If interrupts are desired, set the TXIE interrupt
enable bit. An interrupt will occur immediately
provided that the GIE and PEIE bits of the
INTCON register are also set.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
7.
Load 8-bit data into the TXREG register. This
will start the transmission.
bit 0
bit 1
bit 7/8
Word 1
bit 0
bit 1
bit 7/8
Word 1
1 T
CY
Stop bit
Start bit
bit 0
Stop bit
Word 2
Word 2
Transmit Shift Reg.
© 2007 Microchip Technology Inc.