PIC16F88

Manufacturer Part NumberPIC16F88
ManufacturerMicrochip Technology Inc.
PIC16F88 datasheet
 
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Page 114/228:

REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

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PIC16F87/88
11.4.2
AUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode. Bit SREN is a “don’t care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR reg-
ister will transfer the data to the RCREG register and if
enable bit RCIE bit is set, the interrupt generated will
wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
TABLE 11-13: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
Name
Bit 7
Bit 6
0Bh, 8Bh,
INTCON
GIE
PEIE
10Bh,18Bh
(1)
0Ch
PIR1
ADIF
18h
RCSTA
SPEN
RX9
1Ah
RCREG
AUSART Receive Data Register
(1)
8Ch
PIE1
ADIE
98h
TXSTA
CSRC
TX9
99h
SPBRG
Baud Rate Generator Register
Legend:
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1:
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
DS30487C-page 112
When setting up a synchronous slave reception, follow
these steps:
1.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2.
If interrupts are desired, set enable bit RCIE.
3.
If 9-bit reception is desired, set bit RX9.
4.
To enable reception, set enable bit CREN.
5.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
6.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7.
Read the 8-bit received data by reading the
RCREG register.
8.
If any error occurred, clear the error by clearing
bit CREN.
9.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF TMR1IF -000 0000 -000 0000
SREN
CREN
ADDEN
FERR
OERR
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
TXEN
SYNC
BRGH
TRMT
Value on
Value on:
Bit 0
all other
POR, BOR
Resets
RBIF
0000 000x 0000 000u
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
 2005 Microchip Technology Inc.