SST89C58-33-C-PI Silicon Storage Technology, Inc., SST89C58-33-C-PI Datasheet
SST89C58-33-C-PI
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SST89C58-33-C-PI Summary of contents
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... IAP • Support External Address Range KByte of Program and Data Memory PRODUCT DESCRIPTION SST89C54 and SST89C58 are members of the FlashFlex51 family of 8-bit microcontrollers. The FlashFlex51 family is a family of embedded microcontroller products designed and manufactured on the state-of-the-art SuperFlash CMOS semiconductor process technology ...
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... Programming a SST89C54/58 ................................................................................................................. 21 Flash Operation Status Detection (Ext. Host Handshake) ....................................................................... 22 In-Application Programming Mode ................................................................................................................ 26 In-Application Programming Mode Clock Source ..................................................................................... 26 IAP Enable Bit ......................................................................................................................................... 26 In-Application Programming Mode Commands ........................................................................................ 26 Polling ...................................................................................................................................................... 29 Interrupt Temination ................................................................................................................................. 30 TIMERS/COUNTERS ........................................................................................................................................... 31 © 2000 Silicon Storage Technology, Inc. FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications 2 344-2 8/00 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications SERIAL I/O (UART) .............................................................................................................................................. 31 WATCHDOG TIMER ............................................................................................................................................ 32 SECURITY LOCK ................................................................................................................................................ 32 Hard Lock ................................................................................................................................................. 32 SoftLock ................................................................................................................................................... 32 Status of the Security Lock ........................................................................................................................... 33 RESET ................................................................................................................................................................ 34 Power-On Reset ........................................................................................................................................... 34 POWER-SAVING MODES ................................................................................................................................... 35 CLOCK INPUT OPTIONS .................................................................................................................................... 37 ELECTRICAL SPECIFICATION ........................................................................................................................... 38 Absolute Maximum Ratings .......................................................................................................................... 38 Operation Range ........................................................................................................................................... 38 Reliability Characteristics .............................................................................................................................. 38 DC Electrical Characteristics ......................................................................................................................... 39 AC Electrical Characteristics ......................................................................................................................... 42 Explanation Of Symbols ...
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... Control Timing XTAL1 XTAL2 © 2000 Silicon Storage Technology, Inc. SuperFlash SuperFlash EEPROM EEPROM 16/32K SFRs CPU Security Lock Interrupt RAM Control 256 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications 8 Port 0 I I/O Port I/O Port 2 WDT 8 I/O 8-bit Port 3 UART 344 ILL B1 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications PIN ASSIGNMENTS 40 (T2) P1 (T2 Ex P1.6 7 40-Pin PDIP 33 P1.7 8 Top View 32 RST 9 31 (RXD) P3 (TXD) P3 (INT0#) P3 (INT1#) P3 (T0) P3 (T1) P3 (WR#) P3 (RD#) P3 XTAL2 18 22 XTAL1 19 21 ...
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... WR#: External Data Memory Write strobe P3[7] O RD#: External Data Memory Read strobe © 2000 Silicon Storage Technology, Inc the data sheet) because of the internal pull-ups. P1( have high the data sheet) because of the internal IL 6 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications , on the IL 344-2 8/00 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications ESCRIPTIONS CONTINUED 1 Symbol Type Name and Functions PSEN# O/I Program Store Enable: PSEN# is the Read strobe to External Program Memory. When the SST89C54/58 are executing from Internal Program Memory, PSEN# is inactive (high). When the device is executing code from ...
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... SFR address location B1h, is set, the second- ary 4 KByte block will be visible by program counter. FFFFh Sector 255 FFC0h Sector 127 F03Fh Sector 0 F000h Primary 8 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications Sector 63 Sector 0 Block 1 (4 KByte) 344 ILL F47.6 Secondary 344-2 8/00 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications EA & SFCF[ FFFFh 4 KByte INTERNAL (Block 1) F000h EFFFh 44 KByte EXTERNAL 4000h 3FFFh 16 KByte INTERNAL (Block 0) 0000h F 5: SST89C54 P M IGURE ROGRAM © 2000 Silicon Storage Technology, Inc. EA & SFCF[ FFFFh 48 KByte EXTERNAL 4000h ...
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... Block 0 (i.e. physical locations 0000h – 0FFFh in the current example) will not be accessible. Block 1 will still also be accessible through F000h – FFFFh. Figures 7 and 8 show re-mapped program memory organization for the SST89C54/58. 10 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications EA FFFFh 64 KByte EXTERNAL 0000h 344 ILL F11 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications Activation and Deactivation of Memory Re-mapping The actual amount of memory that is re-mapped is controlled by MAP_EN[1:0] bits as shown in Table 2. The MAP_EN[1:0] bits are the same bits as SFCF[1:0]. The MAP_EN[1:0] bits are under software control and can be changed during program execution. Since changing re- ...
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... INTERNAL (Block 1) F000h 32 KByte EXTERNAL 28 KByte EXTERNAL 8000h 8000h 7FFFh 31/30/28 31/30/28 KByte KByte INTERNAL INTERNAL (Block 0) (Block 0) 1/2/4 KByte 1/2/4 KByte INTERNAL INTERNAL (Block 1) (Block 1) 0000h 0000h ROGRAM EMORY RGANIZATION 12 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications 344 ILL F35.3 344 ILL F36.1 344-2 8/00 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications Data Memory SST89C54/58 have 256 x 8 bits of on-chip RAM and can address KBytes of external data memory. Special Function Registers (SFR) Most of the unique features of the FlashFlex51 microcontroller family are controlled by bits in special function registers (SFRs) located in the FlashFlex51 SFR Memory Map shown below ...
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... SuperFlash Data Register SuperFlash Low Order Byte Address Register – (SFAL) SuperFlash High Order Byte Address Register – A15 to A8 (SFAH SECD0 – Busy Flash_busy 14 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications RESET LSB Value BUSY Flash_busy - - xxx00000b - - MAP_EN 000000xxb 344 PGM T3B ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications SuperFlash Configuration Register (SFCF) Location 7 6 0B1h VIS IAPEN Symbol Function VIS Upper flash block visibility KByte flash block visible from F000-FFFF KByte flash block not visible. IAPEN Enable IAP operation. 1: IAP commands are enabled. ...
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... Mailbox register for interfacing with flash memory block. (High order address register). © 2000 Silicon Storage Technology, Inc SuperFlash Data Register FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications 1 0 Reset Value 00000000b 1 0 Reset Value 00000000b 1 0 Reset Value 00000000b 344-2 8/00 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications SFR ABLE C ATCHDOG IMER S WDTC* Watchdog Timer C0h Control WDTD Watchdog Timer 86h Data/Reload * = Bit Addressable SFRs Watchdog Timer Control Register (WDTC) Location 7 6 0C0h – – Symbol Function WDRE Watchdog timer reset enable. ...
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... READ-ID is performed. In External Host Mode, the internal Flash memory blocks are accessed through the re-assigned I/O port pins (see Figure 9 for details external host, such as an MCU programmer, PCB tester controlled development board. 18 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications Timer 0 00h C/ ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications When the chip is in the External Host Mode, Port 0 pins are assigned to be the parallel data input and output pins. Port 1 pins are assigned to be the non-multiplexed low order address bus signals for the internal flash memory (A7-A0) ...
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... Security lock is enabled on the selected memory block. The selection of the memory sector to be erased is determined by P1[7:6] (A7 & A6), P2[5:0] (A13- A8) and P3[5:4] (A15 & A14). The SECTOR-ERASE command is selected by the binary code of 10b on P3[7:6] and 11b on P2[7:6]. See Figure 13 for timing waveforms. 20 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications 344-2 8/00 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications The BYTE-PROGRAM and BURST-PROGRAM com- mands are used for programming new data into the memory array. Selection of which Program command to use will be dependent upon the desired programming field size. Programming will not take place if any security locks are enabled on the selected memory block ...
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... ALE/ PROG# (i.e. any Erase or Program command); 3) Wait for time out limit expires (20 µs); when programming the next byte 0000b 0000b 0030h 0031h BFh E4h/E2h 22 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications 344 ILL F02.5 344-2 8/00 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications T SU RST PSEN# ALE/PROG# EA# P3[3] P3[7:6], P2[7: IGURE HIP RASE Erase both flash memory blocks. Security lock is ignored and the security bits are erased too RST PSEN# ALE/PROG# EA# P3[3] P3[7:6], P2[7:6] P3[5:4], P2[5: IGURE LOCK RASE Erase one of the flash memory blocks, if the security lock is not activated on that flash memory block. The highest address bits A[15:12] determines which block is erased. For example, if A15 is “ ...
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... Program the addressed code byte if the byte location has been successfully erased and not yet programmed. Byte- Program operation is only allowed when the security lock is not activated on that flash memory block. © 2000 Silicon Storage Technology, Inc. SST89C54 / SST89C58 Preliminary Specifications T ES ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications T SU RST T ES PSEN# T ADS ALE/PROG# T PROG EA# P3[3] row address row address byte address byte address P0 P3[7:6], P2[7:6] 16K/32K Block 4K Block F 15 IGURE URST ROGRAM Program the entire addressed row by burst programming each byte sequentially within the row if the byte location has been successfully erased and not yet programmed ...
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... The critical timing for all Erase and Program commands, is self-generated by the on-chip flash controller unit. © 2000 Silicon Storage Technology, Inc. SST89C54 / SST89C58 Preliminary Specifications The two Program commands are for programming new data into the memory array. The portion of the memory array to be programmed should be in the erased state, FFh ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications IAP Enable Erase 32 KBlock Erase 4 KBlock OR MOV SFAH, #00h MOV SFAH, #F0h Set-Up MOV SFDT, #55h Polling scheme Interrupt scheme MOV SFCM, #0Dh MOV SFCM, #8Dh SFST[2] indicates INT1# occurrence operation completion indicates completion The SECTOR-ERASE command erases all of the bytes in a sector ...
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... These com- mands only change the Re-Map[1:0] bits and have no effect on MAP_EN[1:0] until after a reset cycle. There- fore, the effect of these commands is not immediate. 28 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications IAP Enable Set-Up MOV SFDT, #55h Program sb2 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications Re-Map bits previously in un-programmed state can be programmed by these commands. The PROG-RB1, PROG-RB0 sequences are as follows: IAP Enable Set-Up MOV SFDT, #55h Program Re-Map [0] Program Re-Map [1] MOV SFCM, #08h MOV SFCM, #09h or MOV SFCM, #88h MOV SFCM, #89h ...
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... P ERIFICATION ARAMETERS Symbol PROG BUP1 T T BUPRCV T BUPTO 30 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications 1 SFDT [7:0] SFCM [6:0] 55h 01h 55h 0Dh X 0Bh DI 0Eh DI 06h DO 0Ch 344 PGM T6.3 Min Max 1.125 ES 0 ADS 11 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications Accessing Internal Memory (EA XTAL1 Port 0 XTAL2 RXD 0 TXD 1 INT0# 2 Port 1 INT1# 3 Port WR# 6 RD# 7 Port 2 EA# ALE / PROG IGURE N PPLICATION ROGRAMMING TIMERS/COUNTERS The SST89C54/58 have three 16-bit registers that can be used as either timers or event counters ...
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... SFCM, executed from a Hard Locked block can be operated on a Soft Locked block: BLOCK-ERASE, SECTOR-ERASE, BYTE-PROGRAM, BURST-PROGRAM and BYTE- VERIFY. In External Host Mode, SoftLock behaves the same as a Hard Lock. 32 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications Internal Reset 344 ILL F10.2 344-2 8/00 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications STATUS OF THE SECURITY LOCK The three bits that indicate the SST89C54/58 security lock status are located in SFST[7:5]. As shown in Figure 19 and Table 8, the three security lock bits control the lock status of the primary and secondary blocks of memory. There are four distinct levels of security lock status ...
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... V ming at an indeterminate location, which may cause corruption in the code of the flash. For more information on system level design techniques, please review De- sign Considerations for the SST FlashFlex51 Family Microcontroller Application Note. 34 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications 2 MOVC allowed ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications POWER-SAVING MODES The SST89C54/58 provides three power saving modes of operation for applications where power consumption is critical. The three power saving modes are: Idle, Power Down and Standby (Stop Clock). Idle Idle mode is entered by a software command which sets the IDL bit in the PCON register ...
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... DD Standby mode is 2.7V. maintained. ALE and PSEN# are maintained at the levels prior to the clock being frozen. 36 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications Exited by Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits Idle mode, after the ISR RETI in- struction program re- ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications CLOCK INPUT OPTIONS Shown in Figure 21 are the input and output of an internal inverting amplifier (XTAL1, XTAL2), which can be config- ured for use as an on-chip oscillator. When driving the device from an external clock source, XTAL2 should be left disconnected and XTAL1 should be driven ...
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... Min. 0 -40 2.7 0 0.25 Minimum Specification Units 10,000 Cycles 100 Years 2000 Volts 200 Volts 100 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications -0.5V to +14.0V -1.0V to +6.5V 50mA Max Unit +70 °C +85 °C 5 MHz 33 MHz 344 PGM T11.0 Test Method MIL-STD-883, Method 1033 JEDEC Standard A103 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications ABLE A LECTRICAL HARACTERISTICS T = O°C + 70°C -40° AMB Symbol Parameter V Input Low Voltage IL V Input High Voltage (ports 0,1,2, Input High Voltage (XTAL1, RST) IH1 V Output Low Voltage OL (Ports 1.5, 1.6, 1.7) V Output Low Voltage ...
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... V < -0 MHz, 25° =0° 70°C amb T =-40°C to +85°C amb Minimum =0° 70°C amb T =-40°C to +85°C amb 40 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications = 0V SS Limits Min Max -0.5 0.7 0. 1.0 0.3 0.45 1.0 0.3 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications NOTES: 1. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the V external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1 -to- 0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 2. Capacitive loading on Ports 0 & ...
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... 433 7T 140 123 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications , Units Variable Min. Max MHz CLCL - 40 (5V) ns CLCL - 25 (3V) ns CLCL - 30 (5V) ns CLCL - 25 (3V) ns CLCL 4T - 100 (5V) ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications AC CHARACTERISTICS Explanation of Symbols Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for ...
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... RITE YCLE Oscillator 12MHz 33MHz Min Max Min Max FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications T WHLH T RHDZ T RHDX A7-A0 FROM PCL INSTR IN A15-A8 FROM PCH 344 ILL F14.3 T WHLH T WHQX A7-A0 FROM PCL INSTR IN A15-A8 FROM PCH 344 ILL F15.3 Units Variable Min ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications -0 IGURE XTERNAL LOCK RIVE T 16 ABLE ERIAL ORT IMING Symbol Parameter T Serial Port Clock Cycle XLXL Time T Output Data Setup QVXH to Clock Rising Edge T Output Data Hold After XHQX Clock Rising Edge ...
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... SST89C54-33-C-NJ SST89C54-33-C-TQJ SST89C54-33-I-PI SST89C54-33-I-NJ SST89C54-33-I-TQJ SST89C58 Valid combinations Part Number SST89C58-33-C-PI SST89C58-33-C-NJ SST89C58-33-C-TQJ SST89C58-33-I-PI SST89C58-33-I-NJ SST89C58-33-I-TQJ Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability and to determine availability of new combinations. ...
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... N: PLCC TQ: TQFP NOTE: The SST89C58 can be substituted for any SST89C54 listing above. NOTE: The SST89C59 can be substituted for any SST89C54 or SST89C58 listing above. * Indicates SST similar function and not direct replacement/socket compatible. © 2000 Silicon Storage Technology, Inc. SST SST89C54 4K Flash, 16K Flash & 256B RAM SST89C58 4K Flash, 32K Flash & ...
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... REF. .630 .050 BSC. .020 Min. .100 .112 .165 .180 (PLCC) 48 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications .600 .625 .530 .557 12˚ 4 places 0˚ 15˚ .008 .012 .600 BSC 40.pdipPI-ILL.6 BOTTOM VIEW .026 .032 44.PLCC.NJ-ILL.6 ...
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... FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications Pin 1 Identifier(s) .80 (either or both) BSC 10.0 BSC 12.0 BSC Note: 1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in mm (min/max). 3. Coplanarity: 0.1 (±0.05) mm. 44 (TQFP) EAD ...
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... Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873 © 2000 Silicon Storage Technology, Inc. SST89C54 / SST89C58 Preliminary Specifications 50 FlashFlex51 MCU 344-2 8/00 ...