SST25LF040A-33-4C-S2A Silicon Storage Technology, Inc., SST25LF040A-33-4C-S2A Datasheet
SST25LF040A-33-4C-S2A
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SST25LF040A-33-4C-S2A Summary of contents
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... SST25LF020A/040A devices operate with a single 3.0- 3.6V power supply. The SST25LF020A devices are offered in an 8-lead SOIC 150 mil body width (SA) package. The SST25LF040A devices are offered in an 8-lead SOIC 200 mil body width (S2A) package. All densities are offered in the 8-contact WSON package. See Figure 1 for the pin assignments. ...
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... Preliminary Specifications UNCTIONAL LOCK IAGRAM Address Buffers and Latches CE# ©2004 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A X - Decoder Control Logic Serial Interface SCK SI SO WP# HOLD# 2 SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1242 B1.0 S71242-03-000 6/04 ...
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... Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A PIN DESCRIPTION CE Top View WP 1242 08-soic P1.0 8- SOIC LEAD FIGURE SSIGNMENTS TABLE ESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input ...
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... HIGH IMPEDANCE SO FIGURE 2: SPI P ROTOCOL ©2004 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A DEVICE OPERATION The SST25LF020A/040A is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is Data ...
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... Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Hold Operation HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal ...
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... Block-Erase instruction completion • Chip-Erase instruction completion ©2004 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. ...
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... Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Block Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table software pro- tected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0 ...
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... Device ID is read with output stream is continuous until terminated by a low to high transition on CE# 12. Device ID = 43H for SST25LF020A and 44H for SST25LF040A ©2004 Silicon Storage Technology, Inc. most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID and Read-Status-Register instructions) ...
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... Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Read (20 MHz) The Read instruction supports MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until ter- minated by a low to high transition on CE#. The internal address pointer will automatically increment until the high- est memory address is reached ...
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... ADD. ADD. ADD. X MSB MSB EQUENCE 10 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A N+1 N+2 N+3 N OUT OUT OUT OUT OUT 1242 F05 ...
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... Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a pro- tected memory area will be ignored. ...
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... Write Disable (WRDI) Instruction to terminate AAI Operation (AAI ROGRAM EQUENCE 12 SST25LF020A / SST25LF040A for the completion of each inter Data Byte 2 05 Read Status Register (RDSR) Instruction to verify end of AAI Operation ...
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... Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the any command sequence ...
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... CE#. See Figure 11 for the RDSR instruction sequence Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB (RDSR) S EQUENCE 14 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Status 1242 F11.0 Register Out S71242-03-000 for CE 6/04 ...
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... Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write- Enable-Latch bit to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE# must be driven high before the WREN instruction is executed. ...
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... TATUS ©2004 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, and BP1 bits in the status reg- ister can all be changed. As long as BPL bit is set ...
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... Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Read-ID The Read-ID instruction identifies the devices as SST25LF020A/040A and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A Following the Read-ID instruction, the manufacturer’ CE# ...
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... V OUT OWER UP IMINGS 18 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A EST = /0.9 V @20 MHz, SO=open =GND Max =GND Max ...
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... Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A TABLE 10 ELIABILITY HARACTERISTICS Symbol Parameter 1 N Endurance END 1 T Data Retention Latch Up LTH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11 ...
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... FIGURE 17 ERIAL UTPUT IMING ©2004 Silicon Storage Technology, Inc. T SCKF T SCKR D IAGRAM T SCKL T OH MSB IAGRAM 20 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A T CPH T T CEH CHS LSB HIGH-Z 1242 F16.0 T CHZ LSB 1242 F17.0 S71242-03-000 6/04 ...
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... Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A CE# SCK SO SI HOLD# FIGURE 18 OLD IMING IAGRAM Max DD Chip selection is not allowed. All commands are rejected by the device. V Min DD FIGURE 19 OWER UP IMING ©2004 Silicon Storage Technology, Inc HHH HLS ...
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... V (0.3V ). Input rise and fall times (10 EFERENCE AVEFORMS TO TESTER TO DUT 1242 F21 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A V HT OUTPUT V LT 1242 F20.0 ) for a logic “0”. Measurement reference points ↔ 90%) are <5 ns. Note Test HT HIGH ...
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... SST25LF020A-33-4I-QA SST25LF020A-33-4I-SAE SST25LF020A-33-4I-QAE SST25LF020A-33-4E-SA SST25LF020A-33-4E-QA SST25LF020A-33-4E-SAE SST25LF020A-33-4E-QAE Valid combinations for SST25LF040A SST25LF040A-33-4C-S2A SST25LF040A-33-4C-QA SST25LF040A-33-4C-S2AE SST25LF040A-33-4C-QAE SST25LF040A-33-4I-S2A SST25LF040A-33-4I-QA SST25LF040A-33-4I-S2AE SST25LF040A-33-4I-QAE SST25LF040A-33-4E-S2A SST25LF040A-33-4E-QA SST25LF040A-33-4E-S2AE SST25LF040A-33-4E-QAE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. © ...
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... Maximum allowable mold flash is 0. the package ends and 0.25 mm between leads LEAD MALL UTLINE NTEGRATED SST ACKAGE ODE ©2004 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A SIDE VIEW 7˚ 4 places 0.51 0.33 1.27 BSC 0.25 0.10 1.75 0.25 1.35 0.19 C (SOIC) 150 IRCUIT ...
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... Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Pin #1 TOP VIEW Identifier 5.40 5.15 5.40 5.15 8.10 7.70 Note: 1. All linear dimensions are in millimeters (max/min). 2. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends and 0.25 mm between leads LEAD MALL UTLINE NTEGRATED SST S2A ACKAGE ODE © ...
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... Added Commercial and Extended temperatures and associated MPNs Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2004 Silicon Storage Technology, Inc. 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A SIDE VIEW 0.25 0.19 5.00 ± 0.10 ...