ZL50410 Zarlink Semiconductor, ZL50410 Datasheet
ZL50410
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ZL50410 Summary of contents
Page 1
... WAN uplink 9th port • a 10/100 Mbps Fast Ethernet (FE) CPU port with Reverse MII interface option • Operates stand-alone or can be cascaded with a second ZL50410 to reach 16 ports • Embedded 2 Mbits (256 KBytes) internal memory • supports byte frames • ...
Page 2
... Backpressure flow control for Half Duplex ports • Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports • Built-in reset logic triggered by system malfunction • Built-In Self Test for internal SRAM • IEEE-1149.1 (JTAG) test port ZL50410 2 Zarlink Semiconductor Inc. Data Sheet ...
Page 3
... The ZL50410 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure to the CPU. The CPU can then failover that link to an alternate link. The ZL50410 supports groups of port trunking/load sharing. Each group can contain ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth ...
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... Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3 Frame Forwarding To and From CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.1 MAC Search 5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4 MAC Address Filtering 5.5 Protocol Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6 Logical Port Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.7 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ZL50410 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... MMAC Reference Clock (REF_CLK) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.4 JTAG Test Clock (TCK) speed requirements 10.2 Clock Generation 10.2.1 MDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2.2 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2.3 Ethernet Interface Clocks 11.0 Hardware Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.2 IEEE 802.3 HUB Management (RFC 1516 11.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.1 ReadableOctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2.1.3 FCSErrors 11.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ZL50410 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... BUF_LIMIT – Frame Buffer Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.3.1.6 FCC – Flow Control Grant Period 12.3.2 (Group 1 Address) VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.1 AVTCL – VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.2 AVTCH – VLAN Type Code Register High 12.3.2.3 PVMAP00_0 – Port 0 Configuration Register ZL50410 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...
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... RDRC1 – WRED Rate Control 12.3.6.7 RDRC2 – WRED Rate Control 12.3.6.8 SFCB – Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.9 C1RS – Class 1 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.10 C2RS – Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.11 C3RS – Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.6.12 AVPML – VLAN Tag Priority Map ZL50410 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Address) Port Mirroring Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.8.1 MIRROR CONTROL – Port Mirror Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.8.2 MIRROR_DEST_MAC[5:0] – Mirror Destination MAC Address 0 100 12.3.8.3 MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0 100 12.3.8.4 RMAC_MIRROR0 – RMAC Mirror 100 ZL50410 Table of Contents 8 Zarlink Semiconductor Inc. Data Sheet ...
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... DA – Dead or Alive Register 114 13.0 Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.1 Absolute Maximum Ratings 115 13.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.4 AC Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4.1 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4.2 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 ZL50410 Table of Contents 9 Zarlink Semiconductor Inc. Data Sheet ...
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... I²C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.4.7 Serial Interface Setup Timing 123 13.4.8 JTAG (IEEE 1149.1-2001 124 14.0 Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.1 July 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.2 November 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.3 February 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.4 August 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.5 November 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ZL50410 Table of Contents 10 Zarlink Semiconductor Inc. Data Sheet ...
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... M2_RX M2_C M2_TX M3_RX M3_C 1.2 Power and Ground Distribution G7-10, H7-10, J7-10, K7-10 D5, D12, E4, E13, M4, M13, N5 D9, H4, H13, N7 ZL50410 P_DAT P_DAT P_DAT P_DAT P_DAT A11 P_DAT P_DAT P_DAT P_DAT P_DAT A10 TSTO ...
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... P4, R4, T4, N1, P1, R1, T1, J4, K3, K2, K1, F4, F3, G2, G1 K16, T15, T12, T9, T5, M[7:0]_CRS_DV Input T2, L1, H1 ZL50410 Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Input & Output signal with Tri-State driver Weak internal pull-up (nominal 100K ohm) (refer to Section 1 ...
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... B16 M9_RXCLK C14, D14, D13, E14, M9_RXD[7:0] F14, F13, G14, G13 A16 M9_TXEN B15 M9_TXER ZL50410 I/O Output, slew Ports [7:0] – Transmit Enable This pin also serves as a bootstrap pin. Output, slew Ports [7:0] – Transmit Data Bit [3:0] Input Ports[7:0] – Collision with pull-down Input or Output Ports[7:0] – ...
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... V DD D5, D12, E4, E13, M4 M13, N5, G7-10, H7-10, J7-10 K7-10 Misc. D1 RESIN# C1 RESETOUT# ZL50410 I/O Input Transmit Clock with pull-up Output Gigabit Transmit Clock Output [15:4] Reserved [3] EEPROM checksum is good [2] Initialization Completed [1] Memory Self Test in progress [0] Initialization started These pins also serve as bootstrap pins. Input JTAG - Test Data In ...
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... GREF_CLK Bootstrap Pins (1= pull-up 0= pull-down) (See “Bootstrap Options” on page 20) D2 TSTOUT[0] C3, D3, C2 TSTOUT[3:1] C5, C4, D4 TSTOUT[6:4] C6 TSTOUT[7] D7 TSTOUT[8] ZL50410 I/O Output MII Management Data Clock I/O-TS MII Management Data I/O with pull-up Input RMAC Reference Clock Input GMAC Reference Clock with pull-up 1 Input (Reset Only) Enable Debounce of STROBE signal Pullup – ...
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... A16, B15 M9_TXEN, M9_TXER 1. External pull-up/down resistors are required on all bootstrap pins for proper operation. Recommend 10K for pull-ups and 1K for pull-downs. ZL50410 I/O Input (Reset Only) Module Detect Pullup: Enable. In this mode, the device will detect the existence of a PHY (for hot swap purpose) ...
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... Signal Mapping and Internal pull-up/Down Configuration The ZL50410 Fast Ethernet access ports (0-7) support 3 interface options: RMII, MII & GPSI. The table below summarizes the interface signals required for each interface and how they relate back to the Pin Symbol name shown in the “Ball Signal Description Table” on page 12. It also specifies whether the internal pull-up/down resistor is present for each pin in the specific operating mode ...
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... The ZL50410 Gigabit Ethernet uplink port (port 9) supports 2 interface options: GMII & MII. The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” on page 12. ...
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... The ZL50410 CPU access support 5 interface options 16-bit parallel, serial+MII (port 8), serial only, and unmanaged serial (with optional EEPROM). The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” on page 12. ...
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... Also, in unmanaged mode, an optional I the device at power-up or reset. TSTOUT[7] selects the EEPROM option. Ethernet Interface The ZL50410 supports module hotswap on all it's ports. This is enabled via TSTOUT[9]. When enabled, bootstrap pins M[7:0]_TXEN (ports 0-7) and M9-TXEN & M9_TXER (port 9) are used to specify the module type to support multiple ethernet interfaces during module hotswap ...
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... Default Switch Configuration and Initialization Sequence The ZL50410 will come out of reset in a default configuration, which will allow for basic L2 switching and automatic MAC address learning. In unmanaged mode, the default configuration will take effect immediately after reset. The default settings can be changed using the optional EEPROM. • ...
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... DiffServ EF code support disabled • No VLAN ID hashing • Per-port Defaults • FE Ports - Link heart beat disabled • CPU Port - 100M/Full Duplex/Flow Control - 8-byte header padding - per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers ZL50410 22 Zarlink Semiconductor Inc. Data Sheet ...
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... Frame Engine (FE) and the external physical device (PHY). It has five interfaces: MII, RMII, GPSI (only for 10M), Reverse MII, or Reverse GPSI (only for 10M). The RMAC of the ZL50410 device meets the IEEE 802.3 specification able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for total transmissions ...
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... TX and RX clocks to the CPU register access mechanism via the 8/16-bit or serial interface. Using the MII interface, the CMAC of the ZL50410 device meets the IEEE 802.3 specification able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for total transmissions ...
Page 25
... Heartbeat Packet Generation and Response The ZL50410 provides the ability to monitor a link and detect a simple link failure. The Link Heart Beat (LHB) packet generation module allows simultaneous tracking of all the RMAC ports. Periodically, a LHB message will be sent for each link when inactivity is detected with in a programmable time period reply is not received in a specified amount of time, the failover detection module will identify a point-to-point failure for that link ...
Page 26
... The CPU interface provides for easy and effective management of the switching system. Figure 3 on page 27 provides an overview of the 8/16-bit interface. Figure 4 on page 28 provides an overview of the SSI interface. Figure 5 on page 29 provides an overview of the SSI+MII interface. ZL50410 ISA Interface Serial 16-bit ...
Page 27
... Index Reg 0 Reg (Addr = 1) (Addr = 0) (Addr = 2) 16-bit Address 8-bit Data Bus Internal Registers Inderect Access Figure 3 - Overview of the 8/16-bit Interface ZL50410 Processor 3-bit Address Bus 8/16-bit Data Bus Address I/O Data MUX Command/ Interrupt CPU Frame Reg Status Reg Reg (Addr = 3) (Addr = 4) ...
Page 28
... Index Reg 0 Reg (Addr = 1) (Addr = 0) (Addr = 2) 16-bit Address 8-bit Data Bus Internal Registers Inderect Access Figure 4 - Overview of the SSI Interface ZL50410 Processor Serial Out Serial In Strobe Interrupt Synchronous Serial Interface 3-bit Address Bus INT 16-bit Data Bus Address I/O Data MUX ...
Page 29
... To indirectly configure the register addressed by the index register(s), a “data” register (address 010b) must be written with the desired 8-bit data. • The ZL50410 supports special register-write in serial and 16-bit mode. This allows CPU to write to two consecutive configuration registers in a single write operation. By writing to bit[14] of configuration ZL50410 ...
Page 30
... To transmit a frame from the CPU with MII interface: • ZL50410 acts as a PHY to provide receive clock (RXCLK) to CPU so the CPU will depend on this receive clock to send packets to ZL50410 • ZL50410 has the ability to halt the receive clock if the receive FIFO of ZL50410 is overflow. Transmitting from CPU to ZL50410 will resume once the receive FIFO of ZL50410 is no longer overflow • ...
Page 31
... I C Interface The I²C interface serves the function of configuring the ZL50410 at boot time. The master is the ZL50410, and the slave is the EEPROM memory. The I²C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the control signals that facilitate the transfer of information from EEPROM to the switch ...
Page 32
... I²C protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. Debounce logic on the clock signal (STROBE) can be turned off to speedup command time bits are used to allow up to eight ZL50410 devices to share the same synchronous serial interface. The ID of each device can be setup by bootstrap. ...
Page 33
... Data to be written or read back Write operation can be aborted in the middle by sending an ABORT pulse to the ZL50410. Read operation can only be aborted before issuing the read command to the ZL50410. A START command is detected when DATAIN is sampled high when STROBE- rise and DATAIN is sampled low when STROBE- fall ...
Page 34
... RMAC ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the GMAC and CPU ports, to map the 8 transmit priorities into 4 multicast queues, the LSB is discarded. The priority mapping can be modified through memory configuration command. The multicast queue that is in FIFO format shares the ZL50410 34 Zarlink Semiconductor Inc. ...
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... Basic Flow Shortly after a frame enters the ZL50410 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding ...
Page 36
... MCT data structure. 5.4 MAC Address Filtering The ZL50410's implementation of intelligent traffic switching provides filters for source and destination MAC addresses. This feature filters unnecessary traffic, thereby providing intelligent control over traffic flows and broadcast traffic. ...
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... MAC address filtering allows the ZL50410 to block an incoming packet to an interface when it sees a specified MAC address in either the source address or destination address of the incoming packet. For example, if your network is congested because of high utilization from a MAC address, you can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem ...
Page 38
... Definition” on page 60). For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The ZL50410 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the ZL50410 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. ...
Page 39
... In addition, coordinating VLAN IDs across multiple switches enables VLANs to extend to multiple switches VLANs are supported in the ZL50410. When tag-based VLAN is enabled, each MAC address is learned with it associated VLAN. ...
Page 40
... IEEE 802.1Q Tag TPID = 0x8100 * Provider Tag TPID = Configurable on per device basis The value of the TPID of the Provider VLAN tag is not assigned in the IEEE 802.1ad standard. The ZL50410 provides a global configurable TPID but only supports the Extreme EtherType TPID (i.e. the stacked VLAN tag cannot equal 0x81-00) ...
Page 41
... The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port. 6.2 Frame Engine Details This section briefly describes the functions of each of the modules of the ZL50410 frame engine. 6.2.1 FCB Manager The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. ...
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... Table 8 shows examples of QoS applications with three transmission priorities, but best effort (P0) traffic may form a fourth class with no bandwidth or latency assurances. GMAC port actually has four total transmission priorities. ZL50410 42 Zarlink Semiconductor Inc. ...
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... It is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. In the ZL50410, each RMAC port will support two total classes, and the GMAC port will support four classes. We will discuss the various modes of scheduling these classes in the next section ...
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... Although traffic shaping is not a primary function of the ZL50410, the chip does implement a shaper for every queue in the GMAC port. Our goal in shaping is to control the average rate of traffic exiting the ZL50410. If shaper is enabled, strict priority will be applied to that queue. The priority between two shaped queue is the same as in strict priority scheduling ...
Page 45
... Such a temporary region is necessary, because when the frame first enters the ZL50410, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying ...
Page 46
... The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. On the other hand, the ZL50410 will still prioritize the received frame disregarding the outgoing port flow control capability frame is classified as high priority still subjected to the WRED, which means the no-loss on the high priority queue is not guaranteed ...
Page 47
... Xon is triggered when a port is currently being flow controlled, and all of that port’s reserved FDB slots have been released. Note that the ZL50410’s per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. ...
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... Features and Restrictions A port group (i.e. trunk) can include physical ports, all of the ports in a group can be in the same ZL50410 or in multiple ZL50410 to form a fault tolerant link. There are eight trunk groups total. Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address and destination MAC address ...
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... VLAN. When a multicast packet is sent in from port 3, the ZL50410 select port 0,1,2,3,4,5 and 6 as potential destination based on the VLAN. Then port 3 and 4 are removed because they belong to the source port group (trunk group 1). Two ports from trunk group 0 will be removed based on the hash key ...
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... DEVICE A 10.0 Clocks 10.1 Clock Requirements 10.1.1 System Clock (SCLK) speed requirement SCLK is the primary clock for the ZL50410 device. The speed requirement is based on the system configuration. Below is a table for a few configuration. Configuration 8 Port 10/100M + 1 port 1000M 6-9 ports 10/100M 1-5 ports 10/100M 10.1.2 RMAC Reference Clock (M_CLK) speed requirement M_CLK MHz clock used for the RMAC ports (ports 0-7) and CPU port (port 8) ...
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... The gigabit port generates an external TXCLK interface clock in GMII mode equal to the 125 MHz GREF_CLK. If the GMAC port is configured in Reverse MII mode, RXCLK is generated from GREF_CLK and is equal to GREF_CLK/2 for 100M mode (no support for 10M Reverse MII mode). GREF_CLK needs MHz clock in this mode. ZL50410 51 Zarlink Semiconductor Inc. Data Sheet ...
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... Hardware Statistics Counters List ZL50410 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the delay exceed discard counter (detected by buffer manager) and the filtering counter (detected by queue manager) ...
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... Late Collision B[29] F-U Notation: X-Y Address in the contain memory X: Size and bits for the counter Y: D Word counter d: 24 bits counter bit [23: bits counter bit [31:24 bits counter bit [23:16] U1: 16 bits counter bit [15: bits counter bit [31:16] u: ZL50410 53 Zarlink Semiconductor Inc. Data Sheet ...
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... No collisions 11.2.1.4 AlignmentErrors Counts number of valid frames received with bad alignment (not byte-aligned). Frame size: No framing error No collisions ZL50410 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< BUF_LIMIT if enabled for this port) > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< ...
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... Frame size: 11.2.1.9 LateEvents Counts number of collision events that occurred late (after LateEventThreshold = 64 bytes). Frame size: Events are also counted by collision counter ZL50410 > 64 bytes, > 1522 bytes if VLAN Tagged; (> 1518 bytes if not VLAN Tagged) (> BUF_LIMIT if enabled for this port) don’t care don’ ...
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... InDiscards Counts number of valid frames received which were discarded (i.e., filtered) by the forwarding process. 11.3.1.4 DelayExceededDiscards Counts number of frames discarded due to excessive transmit delay through the bridge. 11.3.1.5 MtuExceededDiscards Counts number of frames discarded due to excessive size. ZL50410 > Jabber 56 Zarlink Semiconductor Inc. Data Sheet ...
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... No collisions: 11.4.1.6 UndersizePkts Counts number of frames received with size less than 64 bytes. Frame size: No FCS error No framing error No collisions ZL50410 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< BUF_LIMIT if enabled for this port) < 64 bytes, 57 Zarlink Semiconductor Inc. Data Sheet ...
Page 58
... Jabbers Counts number of frames received with size exceeding maximum frame size and with bad FCS. Frame size: Framing error No collisions ZL50410 > 1522 bytes if VLAN Tagged; (> 1518 bytes if not VLAN Tagged) (> BUF_LIMIT if enabled for this port) don’t care don’t care < ...
Page 59
... Miscellaneous Counters In addition to the statistics groups defined in previous sections, the ZL50410 has other statistics counters for its own purposes. We have two counters for flow control – one counting the number of flow control frames received, and another counting the number of flow control frames sent. We also have two counters, one for unicast frames sent, and one for non-unicast frames sent. A broadcast or multicast frame qualifies as non-unicast. Furthermore, we have a counter called “ ...
Page 60
... Register Definition 12.1 ZL50410 Register Description Register 0. ETHERNET Port Control Registers (Substitute [n] with Port number (0..9)) ECR1Pn Port Control Register 1 for Port n ECR2Pn Port Control Register 2 for Port n ECR3Pn Port Control Register 3 for Port n ECR4Pn Port Control Register 4 for Port n BUF_LIMIT Frame Buffer Limit ...
Page 61
... Increment MAC port 4,5 address MAC67 Increment MAC port 6,7 address MAC9 Port 9 MAC address byte 5 CPUQINS[6:0] CPUQINSRPT CPUGRNHDL[1:0] CPURLSINFO[4:0] CPUGRNCTR 4. Search Engine Configurations AGETIME_LOW MAC Address Aging Time Low Table 13 - Register Description (continued) ZL50410 CPU Addr R/W (Hex) 220+n R/W 228+2n R/W 229+2n R/W 300 R/W 301 R/W 302 R/W 303 ...
Page 62
... TOS Priority Map High TOSDML TOS Discard Map USER_PROTOCOL_n User Define Protocol n USER_PROTOCOL_ User Define Protocol 0 To FORCE_DISCARD 7 Force Discard Enable WLPP10 Well Known Logic Port 0 and 1 Priority Table 13 - Register Description (continued) ZL50410 CPU Addr R/W (Hex) 401 R/W 403 R/W 500 R/W 510 R/W 511 ...
Page 63
... RHIGHL User Define Range High Bit [7:0] RHIGHH User Define Range High Bit [15:8] RPRIORITY User Define Range Priority 6. MISC Configuration Register MII_OP0 MII Register Option 0 MII_OP1 MII Register Option 1 Table 13 - Register Description (continued) ZL50410 CPU Addr R/W (Hex) 561 R/W 562 R/W 563 R/W 564 R/W 565 R/W ...
Page 64
... Port Mirroring Controls MIRROR_DEST_MAC0 Mirror Destination MAC Address 0 MIRROR_DEST_MAC1 Mirror Destination MAC Address 1 MIRROR_DEST_MAC2 Mirror Destination MAC Address 2 MIRROR_DEST_MAC3 Mirror Destination MAC Address 3 MIRROR_DEST_MAC4 Mirror Destination MAC Address 4 Table 13 - Register Description (continued) ZL50410 CPU Addr R/W (Hex) 602 R/W 603 R/W 604 R/W 605 R/W 606 R/W 607 RO 608 ...
Page 65
... Port Reservation for CPU Port PRG Port Reservation for GMAC Port PTH100_n Port Threshold for RMAC Ports (n=0..7) PTH100_CPU Port Threshold for CPU Port PTHG Port Threshold for GMAC Port Table 13 - Register Description (continued) ZL50410 CPU Addr R/W (Hex) 705 R/W 706 R/W 707 R/W 708 R/W 709 R/W 70A ...
Page 66
... Ports Queue Control Status QCTRL Ports Queue Control BMBISTR0 Memory bist result BMBISTR1 Memory bist result BMControl Memory control BUFF_RST Buffer Reset Pool FCBHEADPTR0 FCB Head Pointer [7:0] Table 13 - Register Description (continued) ZL50410 CPU Addr R/W (Hex) 880+n R/W E00 R/W E01 R/W E02 R/O E03 R/O E10 ...
Page 67
... In 8-bit mode: Address bits [7:0] 12.2.2 INDEX_REG1 (only needed for 8-bit mode) • Address for indirectly accessed register addresses (8 bits) • Address = 1 (write only) • In 16-bit or serial mode: NA • In 8-bit mode: Address bits [15:8] ZL50410 CPU Addr Description (Hex) EC2 EC3 EC4 EC5 EC6 EC7 EC8 ...
Page 68
... CPU has to wait until this bit read a new control command Bit [3]: Transmit FIFO has data for CPU to read (TXFIFO_RDY) Bit [4]: Receive FIFO has space for incoming CPU frame (RXFIFO_SPOK) Bit [5]: Transmit FIFO End Of Frame (TXFIFO_EOF) Bits [7:6]: Reserved ZL50410 68 Zarlink Semiconductor Inc. Data Sheet ...
Page 69
... Accessed by CPU and I²C (R/W) Port 0 – 7 & 9: (RMAC & GMAC Ports) Bit [0] Flow Control 0 - Enable (Default Disable Bit [1] Duplex Mode 0 - Full Duplex (Default Half Duplex - Only in 10/100 mode Bit [2] Speed 0 - 100 Mbps (Default Mbps ZL50410 69 Zarlink Semiconductor Inc. Data Sheet ...
Page 70
... The configuration in ECR1Pn[2:0] is used for (speed/duplex/flow control) setup MII Port Down Note: Bit [4] must be ‘1’. Bit [4] Must be ‘1’. ZL50410 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. Frame is forwarded. Source MAC address is learned. (Default) Frame is dropped Frame is dropped Frame is dropped ...
Page 71
... VLAN mode (PVMODE[0]=’0’), this bit must be 0. Bit [5] Do not change VLAN tag. This overrides PVMAPnn_3 bit [2]. If this bit is set, no tag will be replaced nor removed. 0: Disable (Default) 1: Enable ZL50410 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. Frame is forwarded. Source MAC address is learned. (Default) 71 Zarlink Semiconductor Inc ...
Page 72
... Bits [7:6] Security Enable. The ZL50410 checks the incoming data for one of the following conditions: • If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress port is not the same as the port associated with the MAC address in the MAC table. ...
Page 73
... MCT and associated with the originating source port. The frame loopback will only work for unicast packets. Bit [6]: Link Heart Beat Receive 0: Disable (Default). Also clears all MAC LHB status. 1: Enable Bit [7]: Soft reset. 0: Normal operation (Default) 1: Reset. Not self clearing. ZL50410 73 Zarlink Semiconductor Inc. Data Sheet ...
Page 74
... Reserved Bit [1]: Enable RXCLK output. Active high 0: Disable (Default) 1: M9_RXCLK pin becomes output in MII mode Note: To configure port 9 with the device providing the interface clocks, you need to tie M9_RXCLK to M9_MTXCLK externally as M9_MTXCLK is not a bidirectional clock. ZL50410 74 Zarlink Semiconductor Inc. Data Sheet ...
Page 75
... CPU Address:h036 Accessed by CPU (R/W) Bits [6:0]: Frame Buffer Limit (max 4 KB). Multiple of 64 bytes (Default 0x40) Bit [7]: Reserved 12.3.1.6 FCC – Flow Control Grant Period CPU Address:h037 Accessed by CPU (R/W) Bits [2:0]: Flow Control Grant Period (Default 0x3) Bits [7:3]: Reserved ZL50410 75 Zarlink Semiconductor Inc. Data Sheet ...
Page 76
... VLAN then PVID is used to replace the packet’s VLAN ID. 12.3.2.4 PVMAP00_1 – Port 0 Configuration Register 1 I²C Address h34, CPU Address:h103 Accessed by CPU and I²C (R/W) In Port based VLAN Mode Bits [1:0]: VLAN Mask for ports (Default 0x3) Bits [7:2]: Reserved (Default 0x3F) ZL50410 76 Zarlink Semiconductor Inc. Data Sheet ...
Page 77
... Force untag out (VLAN tagging is based on IEEE 802.1Q rule Disable (Default Force untagged output. All packets transmitted from this port are untagged. This bit is used when this port is connected to legacy equipment that does not support VLAN tagging. ZL50410 77 Zarlink Semiconductor Inc. Data Sheet ...
Page 78
... Same function as SE_OPMODE bit [7]. Either bit can enable the function; both need to be turned off to disable the feature. Bit [2]: Disable dropping of frames with destination MAC addresses 01-80-C2-00-00-01 to 0x01-80-C2-00-00-0F. 0: Drop all frames in this range (Default) 1: Disable dropping of frames in this range ZL50410 78 Zarlink Semiconductor Inc. Data Sheet ...
Page 79
... IP packet with logical port number matching logical port numbers to CPU. 12.3.3 (Group 2 Address) Port Trunking Groups Trunk Group – eight RMAC ports can be selected for each trunk group. 12.3.3.1 TRUNKn– Trunk Group 0~7 CPU Address:h200 trunk group) Accessed by CPU (R/W) Bit [7:0] Port 7-0 bit map of trunk n. (Default 0) ZL50410 ...
Page 80
... Hash result 5 destination port number (Default 0) 12.3.3.5 TRUNKn_HASH76 – Trunk group n hash result 7/6 destination port number CPU Address:h20B+ trunk group) Accessed by CPU (R/W) Bits [3:0] Hash result 6 destination port number (Default 0) Bits [7:4] Hash result 7 destination port number (Default 0) ZL50410 80 Zarlink Semiconductor Inc. Data Sheet ...
Page 81
... Hash Value =4 Hash Value =5 Hash Value =6 Hash Value =7 12.3.3.7 MULTICAST_HASHn-0 – Multicast hash result 0~7 mask byte 0 CPU Address:h228+ hash value) Accessed by CPU (R/W) Bits [7:0]: Port 7-0 bit map for multicast hash. (Default 0xFF) ZL50410 HASH0-1 HASH0-0 HASH1-1 HASH1-0 HASH2-1 HASH2-0 HASH3-1 HASH3-0 HASH4-1 HASH4-0 ...
Page 82
... MAC5 to MAC0 registers form the CPU MAC address. When a packet with destination MAC address match MAC [5:0], the packet is forwarded to the CPU. The default MAC address is 00-00-00-00-00-00. 12.3.4.1 MAC0 – CPU MAC address byte 0 CPU Address:h300 Accessed by CPU (R/W) Bits [7:0]: Byte 0 (bits [7:0]) of the CPU MAC address (Default 0) ZL50410 MAC3 MAC2 MAC1 MAC0 82 Zarlink Semiconductor Inc. Data Sheet ...
Page 83
... INT_MASK0 – Interrupt Mask CPU Address:h306 Accessed by CPU (R/W) The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted. (Default 0x00 Mask the interrupt - 0: Unmask the interrupt (Enable interrupt) (Default) ZL50410 83 Zarlink Semiconductor Inc. Data Sheet ...
Page 84
... INTP_MASK4 CPU Address:h314 (Port CPU,GMAC) 12.3.4.10 RQS – Receive Queue Select CPU Address:h323 Accessed by CPU (RW) Select which receive queue is being used by the CPU port. Note: Strict priority applies between different selected queues (UQ3>UQ2>UQ1>UQ0>MQ3>MQ2>MQ1>MQ0). ZL50410 84 Zarlink Semiconductor Inc. Data Sheet ...
Page 85
... MAC01, MAC23, MAC45, MAC67, and MAC9 registers are used with the MAC0~5 registers to form the CPU MAC address on a per port basis. 12.3.4.13 MAC23 – Increment MAC port 2,3 address CPU Address:h326 Accessed by CPU (RW) Bits [2:0]: Bits [42:40] of Port 2 CPU MAC address Bit [3]: Reserved ZL50410 85 Zarlink Semiconductor Inc. Data Sheet ...
Page 86
... Reserved 12.3.4.16 MAC9 – Increment MAC port 9 address CPU Address:h329 Accessed by CPU (RW) Bits [7:0]: Bits [47:40] of Port 9 CPU MAC address 12.3.4.17 CPUQINS0 - CPUQINS6 – CPU Queue Insertion Command CPU Address:h330-336 Accessed by CPU, (R/W) 55 CQ6 CQ5 ZL50410 CQ4 CQ3 CQ2 86 Zarlink Semiconductor Inc. Data Sheet 0 CQ1 CQ0 ...
Page 87
... CPUGRNHDL0 - CPUGRNHDL1 – CPU Allocated Granule Pointer CPU Address:h338-339 Accessed by CPU, (RO) CPU Queue insertion command Granule pointer. Bits [14:0]: Pointer valid Bit [15]: 12.3.4.20 CPURLSINFO0 - CPURLSINFO4 – Receive Queue Status CPU Address:h33A-33E Accessed by CPU, (R/W) CR4 ZL50410 15 0 CG1 CG0 CR3 CR2 CR1 CR0 87 Zarlink Semiconductor Inc. Data Sheet 0 ...
Page 88
... AGETIME_LOW – MAC address aging time Low I²C Address h049; CPU Address:h400 Accessed by CPU and I²C (R/W) Used in conjuction with AGETIME_HIGH. The ZL50410 removes the MAC address from the data base and sends a Delete MAC Address Control Command to the CPU. Bits [7:0]: Low byte of the MAC address aging timer (Default 0x5C) 12 ...
Page 89
... Enable slow learning. Learning is temporary disabled when search demand is high 12.3.6 (Group 5 Address) Buffer Control/QOS Group 12.3.6.1 QOSC – QOS Control I²C Address h04B; CPU Address:h500 2 Accessed by CPU and I C (R/W) Bit [0]: Enable TX rate control (on RMAC ports only) 0 – Disable (Default) 1 – Enable ZL50410 89 Zarlink Semiconductor Inc. Data Sheet ...
Page 90
... MCCTH – Multicast Threshold Control CPU Address: 512 Accessed by CPU (R/W) Threshold on the multicast granule count. Exceeding the threshold consider as Bits [7:0]: multicast resource low and the new multicast will be dropped flow con- trol is triggered if enabled. (Default: 0x3) ZL50410 90 Zarlink Semiconductor Inc. Data Sheet ...
Page 91
... Corresponds to the frame drop percentage RA% for ingress rate control. Granularity 6.25%. 12.3.6.8 SFCB – Share FCB Size I²C Address h074, CPU Address 518 Accessed by CPU and I²C (R/W) Bits [7:0]: Expressed in multiples of 16 granules. Buffer reservation for shared pool. ZL50410 91 Zarlink Semiconductor Inc. Data Sheet ...
Page 92
... VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used inside the ZL50410. When the packet goes out it carries the original priority. Bits [2:0]: ...
Page 93
... Frame drop priority when VLAN Tag priority field is 4 (Default 0) Bit [5]: Frame drop priority when VLAN Tag priority field is 5 (Default 0) Bit [6]: Frame drop priority when VLAN Tag priority field is 6 (Default 0) Bit [7]: Frame drop priority when VLAN Tag priority field is 7 (Default 0) ZL50410 93 Zarlink Semiconductor Inc. Data Sheet ...
Page 94
... Map TOS into frame discard when low priority buffer usage is above threshold Bit [0]: Frame drop priority when TOS field is 0 (Default 0) Bit [1]: Frame drop priority when TOS field is 1 (Default 0) Bit [2]: Frame drop priority when TOS field is 2 (Default 0) ZL50410 94 Zarlink Semiconductor Inc. Data Sheet ...
Page 95
... Enable Protocol 7 Force Discard User Defined Logical Ports and Well Known Ports The ZL50410 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: • ...
Page 96
... Accessed by CPU and I²C (R/W) Bits [3:0]: Priority setting, transmission + dropping, for Well known port 4 (111 for sun remote procedure call) Bits [7:4]: Priority setting, transmission + dropping, for Well known port 5 (22555 for IP Phone call setup) ZL50410 be programmed via WELL_KNOWN_PORT[7:0]_PRIORITY 96 Zarlink Semiconductor Inc. ...
Page 97
... Bit [3]: Enable Well Known Port 3 Force Discard Bit [4]: Enable Well Known Port 4 Force Discard Bit [5]: Enable Well Known Port 5 Force Discard Bit [6]: Enable Well Known Port 6 Force Discard Bit [7]: Enable Well Known Port 7 Force Discard ZL50410 97 Zarlink Semiconductor Inc. Data Sheet ...
Page 98
... USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority I²C Address h0A4, CPU Address 592 Accessed by CPU and I²C (R/W) Bits [3:0]: Priority setting, transmission + dropping, for logic port 4 Bits [7:4]: Priority setting, transmission + dropping, for logic port 5 (Default 00) ZL50410 0 TCP/UDP Logic Port Low 0 TCP/UDP Logic Port High 98 Zarlink Semiconductor Inc. ...
Page 99
... Enable User Port 2 Force Discard Bit [3]: Enable User Port 3 Force Discard Bit [4]: Enable User Port 4 Force Discard Bit [5]: Enable User Port 5 Force Discard Bit [6]: Enable User Port 6 Force Discard Bit [7]: Enable User Port 7 Force Discard ZL50410 99 Zarlink Semiconductor Inc. Data Sheet ...
Page 100
... RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bit [0]: Drop Priority (inclusive only) Bits [3:1] Transmit Priority (inclusive only) Bits [5:4] Reserved Bits [7: Filtering 01 - Exclusive Filtering (x<=RLOW or x>=RHIGH Inclusive Filtering (RLOW<x<RHIGH Invalid ZL50410 100 Zarlink Semiconductor Inc. Data Sheet ...
Page 101
... Accessed by CPU and I²C (R/W) Bit [0]: Statistic Counter 0 – Disable (Default) 1 – Enable (all ports) When statistic counter is enable, an interrupt control frame is generated to the CPU, every time a counter wraps around. This feature requires an external CPU. ZL50410 101 Zarlink Semiconductor Inc. Data Sheet ...
Page 102
... MII Management state machine and MIIC & MIID PHY register accesses. Bit [7]: MCT Link List structure 0 – Enable (Default) 1 – Disable 12.3.7.4 MIIC0 – MII Command Register 0 CPU Address:h603 Accessed by CPU (R/W) Bits [7:0]: MII Command Data [7:0] ZL50410 102 Zarlink Semiconductor Inc. Data Sheet ...
Page 103
... Note : Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. Writing this register will initiate a serial management cycle to the MII management interface. 12.3.7.8 MIID0 – MII Data Register 0 CPU Address:h607 Accessed by CPU (RO) Bits [7:0]: MII Data [7:0] ZL50410 103 Zarlink Semiconductor Inc. Data Sheet ...
Page 104
... I²C Address 0FF, CPU Address:h60B Accessed by CPU and I²C (R/W) Bits [7:0]: Checksum content (Default 0) This register is used in unmanaged mode only. Before requesting that the ZL50410 updates the EEPROM device, the correct checksum needs to be calculated and written into this checksum register. ZL50410 104 Zarlink Semiconductor Inc ...
Page 105
... FF I²C register = When the ZL50410 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the ZL50410 does not start and pin CHECKSUM_OK is set to zero. 12.3.7.13 LHBTimer – Link Heart Beat Timeout Timer CPU Address:h610 Accessed by CPU (R/W) In slot time (512 bit time) ...
Page 106
... MIRROR_DEST_MAC[5:0] – Mirror Destination MAC Address 0~5 CPU Address 700-705 Accessed by CPU (R/W) DEST_MAC5 DEST_MAC4 [47:40] [39:32] (Default 00) (Default 00) 12.3.8.3 MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0~5 CPU Address 706-70B Accessed by CPU (R/W) SRC_MAC5 SRC_MAC4 [47:40] [39:32] (Default 00) (Default 00) ZL50410 DEST_MAC3 DEST_MAC2 DEST_MAC1 [31:24] [23:16] [15:8] (Default 00) (Default 00) (Default 00) SRC_MAC3 SRC_MAC2 SRC_MAC1 [31:24] [23:16] [15:8] (Default 00) (Default 00) (Default 00) 106 Zarlink Semiconductor Inc ...
Page 107
... To disable this function, program U2MR to 0. (Default = 0) Bits [6:4]: Time Base for Unicast to Multicast, Multicast and Broadcast rate control of Port n: (Default = 000) 000 = 100 us 001 = 200 us 010 = 400 us 011 = 800 us 100 = 1.6 ms 101 = 3.2 ms 110 = 6.4 ms 111 = 12.8 ms Bit [7]: Reserved ZL50410 107 Zarlink Semiconductor Inc. Data Sheet ...
Page 108
... PTH100_CPU – Port CPU Threshold I²C Address h0CB, CPU Address 868 Accessed by CPU and I²C (R/W) Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop or flow control (Default 0x3) ZL50410 108 Zarlink Semiconductor Inc. Data Sheet ...
Page 109
... Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue size exceeds the L1 threshold, received frame will subject to X% (high drop (low drop) WRED. When the queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED. ZL50410 2 C Address h088, CPU Address 890) ...
Page 110
... NOTE: Device Manufacturing test registers. 12.3.10.1 DTSRL – Test Output Selection CPU Address E00 Accessed by CPU (R/W) Test group selection for testout[7:0]. 12.3.10.2 DTSRM – Test Output Selection CPU Address E01 Accessed by CPU (R/W) Test group selection for testout[15:8]. ZL50410 110 Zarlink Semiconductor Inc. Data Sheet ...
Page 111
... Accessed by CPU (RO) TX FSM NOT idle for 5 sec Bit [0]: TX FIFO control NOT idle for 5 sec Bit [1]: RX SFD detection NOT idle for 5 sec Bit [2]: RXINF NOT idle for 5 sec Bit [3]: ZL50410 23 15 BT2 BT1 111 Zarlink Semiconductor Inc. Data Sheet 0 ...
Page 112
... Bit [3]: Reserved Bit [4]: priority queue 1 reach L1 WRED level Bit [5]: priority queue 1 reach L2 WRED level Bit [6]: priority queue 2 reach L1 WRED level Bit [7]: priority queue 2 reach L2 WRED level Bit [8]: priority queue 3 reach L1 WRED level ZL50410 PQSTB PQSTA 112 Zarlink Semiconductor Inc. Data Sheet 0 ...
Page 113
... Priority queue 3 reach L1 WRED level Bit [9]: Priority queue 3 reach L2 WRED level Bit [10]: Priority 0 MC queue full Bit [11]: Priority 1 MC queue full Bit [12]: Priority 2 MC queue full Bit [13]: Priority 3 MC queue full Bits [15:14]: Reserved ZL50410 0 PQSTA 113 Zarlink Semiconductor Inc. Data Sheet ...
Page 114
... CPU Address EB0+n Accessed by CPU (R/W) Bit [0]: Suspend port scheduling (no departure) Bit [1]: Reset queue Bits [4:2]: Reserved Bit [5]: Force out MAC control frame Bit [6]: Force out XOFF flow control frame Bit [7]: Force out XON flow control frame ZL50410 114 Zarlink Semiconductor Inc. Data Sheet ...
Page 115
... BMBISTR0, BMBISTR1 CPU Address EBB, EBC Accessed by CPU (RO) 12.3.10.15 BMControl CPU Address EBD Accessed by CPU (R/W) Bits [3:0]: Block Memory redundancy control 0: Use hardware detected value All others: Overwrite the hardware detected memory swap map Bits [7:4]: Reserved ZL50410 115 Zarlink Semiconductor Inc. Data Sheet ...
Page 116
... Bits [7:0] CPU address EC2 Accessed by CPU (R/W) Fcb_head_ptr[14:8]. The head pointer of free granule link that CPU assigns. Bits [6:0] Set 1 to write Bit [7] If CPU wants to write again, CPU has to clear bit 15 and then set bit 15. ZL50410 116 Zarlink Semiconductor Inc. Data Sheet ...
Page 117
... The information of BM release FIFO is relocated to registers BM_RLSFF_INFO (address ECD, ECC, ECB, ECA, EC9 and EC8). If the FIFO is not empty, CPU can read out the next by setting the bit 0. Read only happens when bit 0 is changing from ZL50410 117 Zarlink Semiconductor Inc. ...
Page 118
... Accessed by CPU (RO) Bits [4:0] Rls_count[6:2] Bit [ then It is multicast packet. Bits [7:6] Rls_src_port[1:0[ CPU address ECD Accessed by CPU (RO) Bits [1:0] Rls_src_port[3:2] Bits [3:2] Class[1:0] Bit [4] This release request is from QM directly. Bits [7:5] Entries count in release FIFO, 0 means FIFO is empty ZL50410 118 Zarlink Semiconductor Inc. Data Sheet ...
Page 119
... Busy reading configuration from I²C 0: Not busy (not reading configuration from I²C) Bit [2]: 1: BIST in progress 0: BIST not running Bit [3]: 1: RAM Error 0: RAM OK Bits [5:4]: Device Signature 11: ZL50410 device Bits [7:6]: Revision 00: Initial Silicon 01: Second Silicon 10: Third Silicon ZL50410 119 Zarlink Semiconductor Inc. Data Sheet ...
Page 120
... Application Note, ZLAN-37. Bit [0] Flow control enable 1: Flow control 0: No flow control Bit [1] Full duplex port 1: Full duplex 0: Half duplex Bit [2] Fast Ethernet port (if bit [5] not set Port Bit [3] Link is down 1: Link down 0: Link up ZL50410 120 Zarlink Semiconductor Inc. Data Sheet ...
Page 121
... Note: If Module Detect feature is disabled (bootstrap TSTOUT[9]=’0’), this bit will always be ‘1’. 12.3.11.6 DA – Dead or Alive Register CPU Address: hFFF Accessed by CPU (RO) Always return 8’ Indicate the CPU interface or serial port connection is good. Bits [7:0] Always return DA ZL50410 121 Zarlink Semiconductor Inc. Data Sheet ...
Page 122
... Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied. 13.2 DC Electrical Characteristics V = 3.3 V +/- 10 1.8 V +/- 5% DD ZL50410 - +150 +125 C +2. +3. +1. + ...
Page 123
... C Output Capacitance OUT C I/O Capacitance I/O Thermal resistance with 0 air flow ja Thermal resistance with 1 m/s air flow ja Thermal resistance with 2 m/s air flow ja Thermal resistance between junction and case jc ZL50410 Min. 2.4 2.0 < < OUT CC 123 Zarlink Semiconductor Inc. Data Sheet Typ. Max. Unit 100 ...
Page 124
... R1 Bootstrap Pins Outputs Figure 13 - Typical Reset & Bootstrap Timing Diagram Symbol Parameter R1 Delay until RESETOUT# is tri-stated R2 Bootstrap stabilization R3 RESETOUT# assertion ZL50410 Tri-Stated R3 Inputs R2 Min. Typ RESETOUT# state is then determined by the external pull-up/down resistor Bootstrap pins sampled on rising edge of ...
Page 125
... T WS Write Active Time T WA Write Hold Time T WH Write Recovery time T WR Data Set Up time T DS Data Hold time T DH ZL50410 Activ e Tim e R ecov ery Tim ATA0 H old tim e ...
Page 126
... Read Active Time T RA Read Hold Time T RH Read Recovery time T RR Data Valid time T DV Data Invalid time T DI Table Characteristics - CPU Read Cycle ZL50410 Activ e Tim e R ecov ery Tim ...
Page 127
... Figure Characteristics – Reduced Media Independent Interface (RX) Symbol M2 M[7:0]_RXD[1:0] Input Setup Time M3 M[7:0]_RXD[1:0] Input Hold Time M4 M[7:0]_CRS_DV Input Setup Time M5 M[7:0]_CRS_DV Input Hold Time M6 M[7:0]_TXEN Output Delay Time M7 M[7:0]_TXD[1:0] Output Delay Time ZL50410 M_CLK M6-max M6-min Mn_TXEN M7-max M7-min Mn_TXD[1:0] M_CLK M2 Mn_RXD M3 M4 Mn_CRS_DV ...
Page 128
... MM3 Mn_RXD[3:0] Input Hold Time MM4 M[9,7:0]_CRS_DV Input Setup Time MM4 M[8]_CRS_DV Input Setup Time MM5 Mn_CRS_DV Input Hold Time MM6 Mn_TXEN Output Delay Time MM7 Mn_TXD[3:0] Output Delay Time ZL50410 Mn_TXCLK MM6-max MM6-min Mn_TXEN MM7-max MM7-min Mn _TXD[3:0] Mn_RXCLK MM2 Mn_RXD[3:0] MM ...
Page 129
... M[7:0]_RXD Input Setup Time SM3 M[7:0]_RXD Input Hold Time SM4 M[7:0]_CRS_DV Input Setup Time SM5 M[7:0]_CRS_DV Input Hold Time SM6 M[7:0]_TXEN Output Delay Time SM7 M[7:0]_TXD Output Delay Time ZL50410 Mn_ TXCLK SM6-max SM6-min Mn_TXEN SM7-max SM7-min Mn_TXD Mn_RXCLK SM2 Mn_RXD ...
Page 130
... Gigabit Media Independent Interface M9_TXD [7:0] Figure Characteristics- Gigabit Media Independent Interface (TX) M9_RXCLK M9_RXCLK M9_RXD[7:0] M9_RXD[7:0] M9_RXDV M9_RXDV M9_RXER M9_RXER M9_RX_CRS M9_RX_CRS Figure Characteristics – Gigabit Media Independent Interface (RX) ZL50410 M9_TXCLK G12-max G12-min G13-max G13-min M9_TXEN G14-max G14-min M9_TXER ...
Page 131
... M9_RXER Input Setup Times G6 M9_RXER Input Hold Times G7 M9_CRS Input Setup Times G8 M9_CRS Input Hold Times G12 M9_TXD[7:0] Output Delay Times G13 M9_TXEN Output Delay Times G14 M9_TXER Output Delay Times ZL50410 125 Mhz Min. (ns) Max. (ns ...
Page 132
... MDIO Input Setup and Hold Timing Figure 24 - MDIO Input Setup and Hold Timing Symbol D1 MDIO input setup time D2 MDIO input hold time D3 MDIO output delay time ZL50410 MDC D1 D2 MDIO MDC D3-max D3-min MDIO Figure 25 - MDIO Output Delay Timing MDC=500 KHz Parameter Min ...
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... I²C Input Setup Timing Symbol S1 SDA input setup time S2 SDA input hold time S3* SDA output delay time * Open Drain Output. Low to High transistor is controlled by external pullup resistor. ZL50410 SCL S1 SDA Figure 26 - I²C Input Setup Timing SCL S3-max S3-min SDA Figure 27 - I²C Output Delay Timing ...
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... STROBE Dataout Figure 29 - Serial Interface Output Delay Timing Symbol D1 DATAIN setup time D2 DATAIN hold time D3 DATAOUT output delay time D4 STROBE low time D5 STROBE high time ZL50410 Figure 28 - Serial Interface Setup Timing D3-max D3-min Parameter Min. (ns ...
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... Symbol Parameter TCK frequency of operation TCK cycle time TCK clock pulse width TRST# assert time J1 TMS, TDI data setup time J2 TMS, TDI data hold time J3 TCK to TDO data valid ZL50410 J1 J2 Figure 30 - JTAG Timing Diagram Min. Typ. Max ...
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... Added section “Default Switch Configuration and Initialization Sequence” on page 21 • Added Private VLAN Edge (protected ports), force VLAN tag out, and unknown IP Multicast filtering support • Updated CPU timing diagrams to clarify P_A timing ZL50410 136 Zarlink Semiconductor Inc. Data Sheet ...
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... TOP VIEW SIDE VIEW c Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE 213730 ACN 14Nov02 DATE APPRD. BOTTOM VIEW b Previous package codes Dimension MIN MAX 1. 0.30 0.50 0.53 REF A2 D 16.90 17.10 E 16.90 17.10 b 0.40 0.60 e 1.00 N 208 Conforms to JEDEC MO-192 Package Code ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...