74LVX541MTCX Fairchild Semiconductor, 74LVX541MTCX Datasheet

IC BUFF/DVR TRI-ST 8BIT 20TSSOP

74LVX541MTCX

Manufacturer Part Number
74LVX541MTCX
Description
IC BUFF/DVR TRI-ST 8BIT 20TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LVXr
Datasheet

Specifications of 74LVX541MTCX

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
8
Current - Output High, Low
4mA, 4mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Logic Family
74LVX
Number Of Channels Per Chip
Octal
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
85 C
Mounting Style
SMD/SMT
High Level Output Current
- 4 mA
Input Bias Current (max)
4 uA
Low Level Output Current
4 mA
Maximum Power Dissipation
180 mW
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
8
Output Type
3-State
Propagation Delay Time
14.9 ns @ 2.7 V or 10.5 ns @ 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2005 Fairchild Semiconductor Corporation
74LVX541M
74LVX541SJ
74LVX541MTC
74LVX541
Low Voltage Octal Buffer/Line Driver with
3-STATE Outputs
General Description
The LVX541 is an octal non-inverting buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver which
provides improved PC board density. The inputs tolerate up
to 7V allowing interface of 5V systems to 3V systems.
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Order Number
OE
I
O
0
Pin Names
0
- I
1
- O
, OE
7
7
2
Package Number
3-STATE Output Enable Inputs
Inputs
3-STATE Outputs
MTC20
M20B
M20D
Descriptions
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
DS500291
Features
Logic Symbol
Truth Table
H
L
Input voltage translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
dynamic threshold performance
LOW Voltage Level
HIGH Voltage Level
Package Description
OE
H
L
X
L
1
Inputs
OE
Z
X
H
L
X
L
IEEE/IEC
2
High Impedance
Immaterial
September 1999
Revised April 2005
H
X
X
L
I
www.fairchildsemi.com
Outputs
H
Z
Z
L

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74LVX541MTCX Summary of contents

Page 1

... Output Enable Inputs Inputs 3-STATE Outputs 0 7 © 2005 Fairchild Semiconductor Corporation Features Input voltage translation from Ideal for low power/low noise 3.3V applications Guaranteed simultaneous switching noise level and dynamic threshold performance Package Description Logic Symbol IEEE/IEC Truth Table Inputs OE OE ...

Page 2

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. Input Voltage ( Output Diode Current ( 0. 0.5V ...

Page 3

AC Electrical Characteristics V CC Symbol Parameter (V) t Propagation Delay 2.7 PLH t Time PHL r 3.3 t 3-STATE Output 2.7 PZL t Enable Time PZH r 3.3 t 3-STATE Output 2.7 PLZ r t Disable Time 3.3 PHZ ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide www.fairchildsemi.com Package Number M20B 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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