M25P05-AVMP6TP Numonyx, B.V., M25P05-AVMP6TP Datasheet - Page 18

• Manufacturer Part Number: M25P05-AVMP6TP
• Description: 512-Kbit, serial flash memory, 50 MHz SPI bus interface
• Manufacturer: Numonyx, B.V.

Instructions
6
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Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
Chip Select (S) must be driven High after the last bit of the instruction sequence has been
shifted in.
In the case of a read data bytes (READ), read data bytes at higher speed (Fast_Read), read
identification (RDID), read status register (RDSR) or release from deep power-down, and
read electronic signature (RES) instruction, the shifted-in instruction sequence is followed
by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out
sequence is being shifted out.
In the case of a page program (PP), sector erase (SE), bulk erase (BE), write status register
(WRSR), write enable (WREN), write disable (WRDI) or deep power-down (DP) instruction,
Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is
rejected, and is not executed. That is, Chip Select (S) must driven High when the number of
clock pulses after Chip Select (S) being driven Low is an exact multiple of eight.
All attempts to access the memory array during a write status register cycle, program cycle
or erase cycle are ignored, and the internal write status register cycle, program cycle or
erase cycle continues unaffected.
Table
4.
M25P05-A