M25P05-AVMN6T NUMONYX, M25P05-AVMN6T Datasheet
M25P05-AVMN6T
Specifications of M25P05-AVMN6T
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M25P05-AVMN6T Summary of contents
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... More than 100,000 Erase/Program Cycles per Sector More than 20 Years’ Data Retention August 2005 512 Kbit, Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface Figure 1. Packages M25P05 SO8 (MN) 150 mil width VDFPN8 (MP) (MLP8) TSSOP8 (DW) ...
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... M25P05-A TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Data Output ( Serial Data Input ( Serial Clock ( Chip Select ( Hold (HOLD Write Protect ( SPI MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Status Register ...
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... POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 INITIAL DELIVERY STATE MAXIMUM RATING AND AC PARAMETERS PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 REVISION HISTORY M25P05-A 3/42 ...
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... M25P05-A SUMMARY DESCRIPTION The M25P05 512 Kbit (64K x 8) Serial Flash Memory, with advanced write protection mecha- nisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 2 sectors, each con- taining 128 pages ...
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... Chip Select (S) driven Low. Write Protect (W). The main purpose of this in- put signal is to freeze the size of the area of mem- ory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). M25P05-A 5/42 ...
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... M25P05-A SPI MODES These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data Figure 4 ...
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... Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits. . CC1 . The device remains in this CC2 Deep Power-down (DP)). This can be used Table M25P05-A 6., that can be 7/42 ...
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... The environments where non-volatile memory de- vices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P05-A fea- tures the following data protection mechanisms: Power On Reset and an internal timer (t can provide protection against inadvertant changes while the power supply is outside the operating specification ...
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... To restart commu- nication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. Hold Condition (standard use) M25P05-A Figure Hold Condition (non-standard use) AI02029D 9/42 ...
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... M25P05-A MEMORY ORGANIZATION The memory is organized as: 65,536 bytes (8 bits each) 2 sectors (256 Kbits, 32768 bytes each) 256 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable ...
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... D8h 1100 0111 C7h 1011 1001 B9h 1010 1011 ABh M25P05-A Dummy Data Bytes Bytes ...
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... M25P05-A Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set pri every Page Program (PP), Sector Erase Figure 8. Write Enable (WREN) Instruction Sequence 12/42 (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction ...
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... Figure 9. Write Disable (WRDI) Instruction Sequence – Power-up – Write Disable (WRDI) instruction completion (Figure 9.) – Write Status Register (WRSR) instruction com- pletion – Page Program (PP) instruction completion – Sector Erase (SE) instruction completion – Bulk Erase (BE) instruction completion Instruction High Impedance M25P05-A AI03750D 13/42 ...
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... M25P05-A Read Identification (RDID) The Read Identification (RDID) instruction is avail- able in products with Process Technology code X only. The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, fol- lowed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for STMicroelectronics. The ...
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... Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) be- come read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for exe- cution Status Register Out MSB M25P05-A Status Register Out MSB AI02031E Table 15/42 ...
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... M25P05-A Write Status Register (WRSR) The Write Status Register (WRSR) instruction al- lows new values to be written to the Status Regis- ter. Before it can be accepted, a Write Enable (WREN) instruction must previously have been ex- ecuted. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL) ...
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... Note defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown Instruction Status Register High Impedance MSB M25P05 AI02282D Memory Content (1) Protected Area Unprotected Area Protected against Ready to accept Page Page Program, Sector Program and Sector Erase and Bulk Erase Erase instructions Protected against Ready to accept Page Page Program, Sector ...
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... M25P05-A Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the mem- ...
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... High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) in- struction, while an Erase, Program or Write cycle Figure 14 progress, is rejected without having any ef- fects on the cycle that is in progress BIT ADDRESS DATA OUT MSB Read Data Bytes at Higher 47 DATA OUT MSB MSB M25P05-A Speed AI04006 19/42 ...
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... M25P05-A Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been ex- ecuted. After the Write Enable (WREN) instruction has been decoded, the device sets the Write En- able Latch (WEL) ...
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... Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP1, BP0) Figure 16. bits (see Data Byte MSB Data Byte 256 MSB AI04082B ) is initiated. While the Sector Erase cy- SE Table 3. and Table 2.) is not executed. M25P05-A 21/42 ...
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... M25P05-A Figure 16. Sector Erase (SE) Instruction Sequence Note: 1. Address bits A23 to A16 must be set to 00h. 22/ Instruction 24 Bit Address 23 22 MSB AI03751D ...
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... At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if both Block Protect (BP1, BP0) bits are 0. The Bulk Figure 17. Erase (BE) instruction is ignored if one, or more, sectors are protected Instruction M25P05-A AI03752D 23/42 ...
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... M25P05-A Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest con- sumption mode (the Deep Power-down mode). It can also be used as a software protection mecha- nism, while the device is not in active use this mode, the device ignores all Write, Program and Erase instructions ...
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... C Instruction D High Impedance Q Note: The value of the 8-bit Electronic Signature, for the M25P05-A, is 05h. The Release from Deep Power-down and Read Electronic Signature (RES) instruction is terminat driving Chip Select (S) High after the Elec- tronic Signature has been read at least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the Electronic Signature to be output repeatedly ...
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... M25P05-A Figure 20. Release from Deep Power-down (RES) Instruction Sequence Instruction D High Impedance Q 26/ RES1 Deep Power-down Mode Stand-by Mode AI04078B ...
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... CC WI after V passed the V (min) level CC CC Table 8. , has elapsed, after V VSL (min), the device can be selected for CC delay is not yet PUW supply. Each CC drops from the CC , all operations are WI Device fully accessible time M25P05-A has risen CC rail CC AI04009C 27/42 ...
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... M25P05-A Table 8. Power-Up Timing and V Symbol (1) V (min low t CC VSL (1) Time delay to Write instruction t PUW (1) Write Inhibit Voltage V WI Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains ...
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... JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ) plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 3 M25P05-A Min. Max. Unit –65 150 °C °C (1) – ...
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... M25P05-A DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests performed under the Measure- Table 10. Operating Conditions Symbol V Supply Voltage ...
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... Bytes 256) Test Condition (in addition to those in Table 0.1V / 0.9.V at 50MHz open C = 0.1V / 0.9.V at 20MHz open 1 –100 A OH Table 10. and Table 11. Parameter Min. M25P05-A Min. Max. Unit 10.) ± 2 µA ± 2 µA 50 µA 5 µ – 0.5 0. 0. –0 Typ. Max. Unit 1 0.4+ n*1/256 0 ...
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... M25P05-A Table 15. AC Characteristics (25MHz Operation) Test conditions specified in Symbol Alt. Clock Frequency for the following instructions: FAST_READ PP, SE, BE, DP, RES, WREN, WRDI, DSR, WRSR f Clock Frequency for READ instructions R (1) t Clock High Time t CLH CH (1) t Clock Low Time t CLL CL (2) ...
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... Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set Details of how to find the date of marking are given in Application Note, AN1995 Table 10. and Parameter 3 (peak to peak) 3 (peak to peak) C M25P05-A (5) Table 11. Min. Typ. Max. D. ...
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... M25P05-A Table 17. AC Characteristics (50MHz Operation) 50MHz available only in products with Process Technology code X Test conditions specified in Symbol Alt. Clock Frequency f f FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI RDID, RDSR, WRSR f Clock Frequency for READ instructions R (1) t Clock High Time t CLH ...
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... Figure 23. Serial Input Timing S tCHSL C tDVCH D High Impedance Q Figure 24. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL High Impedance Q tSLCH tCHSH tCHDX tCLCH MSB IN M25P05-A tSHSL tSHCH tCHCL LSB IN AI01447C tSHWL AI07439 35/42 ...
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... M25P05-A Figure 25. Hold Timing HOLD Figure 26. Output Timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D 36/42 tHLCH tCHHL tCHHH tHLQZ tCH tCLQV tQLQH tQHQL tHHCH tHHQX AI02032 tCL tSHQZ LSB OUT AI01449e ...
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... M25P05 45˚ SO-A inches Typ Min 0.053 0.004 0.043 0.013 0.007 0.189 0.150 0.050 – 0.228 0.010 0.016 0° 8 Max 0 ...
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... M25P05-A Figure 28. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, Package Outline Note: Drawing is not to scale. Table 19. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, Package Mechanical Data Symbol Typ 0.65 A3 0.20 b 0.40 D 6.00 D1 5.75 D2 3.40 E 5. ...
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... M25P05 TSSOP8AM inches Typ Min 0.0020 0.0394 0.0315 0.0075 0.0035 0.1181 0.1142 0.0256 – 0.2520 0.2441 0.1732 0.1693 0.0236 0.0177 0.0394 0° ...
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... Note: 1. The TSSOP8 package is available in products with Process Technology code X only (details of how to find the process on the device marking are given in Application Note AN1995). For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 40/42 M25P05 ...
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... CC3 SE (Read Identification (RDID) and and Note 1 added. changed, note 2 and T values removed. LEAD Table 13., DC Characteristics. and Release from Deep Power-down and Active Power, Standby Power and Deep and Table 18.) Page Programming, Page Program (PP) M25P05-A (typ) BE Table 17., AC and 41/42 ...
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... M25P05-A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...