M25PE40-VMP6TP Numonyx, B.V., M25PE40-VMP6TP Datasheet - Page 19

• Manufacturer Part Number: M25PE40-VMP6TP
• Description: 4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout
• Manufacturer: Numonyx, B.V.

M25PE40
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(FAST_READ), Read Status Register (RDSR) or Read to Lock Register (RDLR) instruction,
the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can
be driven High after any bit of the data-out sequence is being shifted out.
In the case of a Page Write (PW), Page Program (PP), Page Erase (PE), Subsector Erase
(SSE), Sector Erase (SE), Bulk Erase (BE), Write Enable (WREN), Write Disable (WRDI),
Write Status Register (WRSR), Write to Lock Register (WRLR), Deep Power-down (DP) or
Release from Deep Power-down (RDP) instruction, Chip Select (S) must be driven High
exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is,
Chip Select (S) must driven High when the number of clock pulses after Chip Select (S)
being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write cycle, Program cycle or Erase cycle
are ignored, and the internal Write cycle, Program cycle or Erase cycle continues
unaffected.
inTable
5.
Instructions
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