T8531TLDB Agere Systems, Inc., T8531TLDB Datasheet
T8531TLDB
Related parts for T8531TLDB
T8531TLDB Summary of contents
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T8531/T8532 Multichannel Programmable Codec Chip Set Features Single 5 V power supply operation Per-channel programmable transmit gain — 25.6 dB range, better than 0.01 dB steps Per-channel programmable receive gain — 17.8 dB range, better than 0.01 dB steps Per-channel ...
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Codec Chip Set Contents Features ..................................................................... 1 General Description.................................................... 1 T8532 Description.................................................... 4 T8531 Description.................................................... 5 Pin Information ........................................................... 7 Chip Set Functional Description ............................... 12 Transmit Path......................................................... 12 Antialias Filter and - Converter ...................... 12 Decimator ........................................................... 12 Digital ...
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February 2002 Tables Table 1. T8532 Pin Descriptions ................................. 8 Table 2. T8531 Pin Descriptions ............................... 10 Table 3. Active Time-Slot Spacing in a PCM Bus Frame ................................................... 15 Table 4. DSP Engine RAM Map for Channel_0 ac Path Coefficients ...
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Codec Chip Set General Description (continued) T8532 Description The T8532 block diagram is shown in Figure 2. Each of its eight channels consists of an antialias filter, sigma-delta A/D and D/A converters, reconstruction and smoothing filters, termination impedance synthesis, and ...
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February 2002 General Description (continued) T8531 Description As shown in Figure 4, the T8531 contains a digital signal processor (DSP) engine surrounded by a customized input/output frame. The I/O frame performs the -law or A-law conversion as well as the ...
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Codec Chip Set General Description (continued) T8531 Description (continued) 8 kHz 8 kHz /A-LAW /A-LAW PCMRX PCMRX RECV RECV TO TO FILTER FILTER LINEAR LINEAR 8 kHz 8 kHz LINEAR LINEAR PCMTX PCMTX XMT FILTER XMT FILTER TO TO /A-LAW ...
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February 2002 Pin Information 64 63 VRTX7 1 VRP7 2 VRN7 SSA VRN6 5 VRP6 6 VRTX6 7 VTX6 DDA VTX5 10 VRTX5 11 VRP5 12 VRN5 SSA VRN4 15 VRP4 ...
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Codec Chip Set Pin Information (continued) Table 1. T8532 Pin Descriptions Number Name Type 64, 8, 10, 18, VTX[7:0] AI 31, 39, 41 11, 17, 32, VRTX[7:0] AI 38, 42 12, 16, 33, VRP[7:0] ...
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February 2002 Pin Information (continued) 64 DSPCKSL2 TDI 4 TDO 5 TMS 6 TCK 7 TSTCLK DDA SSA NC 14 ...
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Codec Chip Set Pin Information (continued) Table 2. T8531 Pin Descriptions Number Name Type 29 UPDI TI 30 UPDO TO 27 UPCK UPCS 43, 45, OSDX[3:0] CI 36, 38 42, 44, OSDR[3: OSCK ...
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February 2002 Pin Information (continued) Table 2. T8531 Pin Descriptions (continued) Number Name 23 SDX 21 SFS 54 CDO 51 CDI 53, 52 CCS[1:0] 7 TCK 4 TDI 5 TDO 6 TMS 48 JTESTB 59 HIGHZB 60 TEST 61 CK16 ...
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Codec Chip Set Chip Set Functional Description Transmit Path Antialias Filter and - Converter The line interface circuit must provide a transmit signal, VTX, and a reference voltage, VRTX, which is the dc voltage of the VTX signal for that ...
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February 2002 Chip Set Functional Description (continued) Receive Path In the receive direction, the signal received from the system interface is converted to a 16-bit linear PCM signal. Receive Path Filtering The 16-bit linear PCM signal is filtered and interpolated ...
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Codec Chip Set Chip Set Functional Description (continued) Other Chip Set Functions (continued) Digital Termination Impedance Synthesis (continued) Alpha bits [9:0] represent the RC time constant of the impedance that the filter is going to synthesize. The bits are formatted ...
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February 2002 Chip Set Functional Description (continued) T8531 Functional Blocks (continued) T8531 System Interface The system interface is a full-duplex interface used for the exchange of PCM data with the system. The sys- tem is the master of this bus. ...
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Codec Chip Set Chip Set Functional Description (continued) T8531 Functional Blocks (continued) A pause therefore exists between the external control- ler issuing an address and receiving a data read back. The data rate of 2.048 MHz allows 256 SCK cycles ...
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February 2002 Chip Set Functional Description (continued) DSP Engine Timing (continued) Control of the DSP Engine via the Microprocessor Interface There are four types of commands that the external controlling device may issue to the DSP engine: 1. Downloading data ...
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Codec Chip Set Chip Set Functional Description (continued) DSP Engine Timing (continued) The Time-Slot Control Word The DSP engine works in time-slot order. The TSA function is performed by the decimator/interpolator. The DSP engine is not required to reorder the ...
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February 2002 Chip Set Functional Description (continued) DSP Engine Timing (continued) Microprocessor Start-Up of the DSP Engine Once the interrupt system is enabled, the DSP engine looks for a read or write interrupt from the microproces- sor interface once every ...
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Codec Chip Set Chip Set Functional Description (continued) DSP Engine Timing (continued) Changing DSP RAM Space of an Active Time Slot The microprocessor is only allowed to change four RAM locations for an active time slot: Relative transmit gain Relative ...
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February 2002 Chip Set Functional Description (continued) T8531 Reset and Start-Up (continued) Internal Reset Internal reset is defined as the process that starts when the internal reset line is brought low. This hap- pens as a consequence of hardware (RTSB) ...
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Codec Chip Set Chip Set Functional Description (continued) Start-Up After Internal Reset Autocalibration Autocalibration is an analog self-test and trimming pro- cedure controlled by the DSP core. Sine wave signals are generated in the receive direction. These signals are looped ...
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February 2002 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other ...
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Codec Chip Set Electrical Characteristics For all specifications – + and Input signal frequency is 1020 Hz, unless otherwise noted. DSP clock frequency is A ...
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February 2002 Electrical Characteristics dc Characteristics (continued) Table 10. T8532 Power Dissipation Parameter Symbol Powerdown Current IDD0 Powerup Current IDD1 Table 11. T8531 Power Dissipation Parameter Symbol Powerdown Current IDD0 Powerup Current IDD1 * Powerup current exhibits a negative temperature ...
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Codec Chip Set Transmission Characteristics Table 12. Gain and Dynamic Range (continued) Parameter Symbol Transmit Gain Variation GXAF with Frequency Transmit Gain Variation GXAL with Signal Level Receive Gain Absolute GRA Accuracy Relative Gain: — VRP to VRN Relative Phase: ...
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February 2002 Transmission Characteristics Table 13. Noise (per Channel) Parameter Symbol Transmit Noise C-message Weighted Transmit Noise P-message Weighted Receive Noise C-message Weighted Receive Noise P-message Weighted Noise, Single Frequency N RS ...
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Codec Chip Set Transmission Characteristics Table 14. Distortion and Group Delay Parameter Symbol Signal to Total Distortion Transmit or Receive C-message Weighted Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion TX Group Delay, Absolute RX Group Delay, Absolute ...
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February 2002 Timing Characteristics A signal is valid above V or below V IH fication, the following conditions apply: All input signals are defined measured from measured ...
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Codec Chip Set Timing Characteristics (continued) TIME SLOT tFSHFSL SFS tSFHSCL tSCLSFL SCK tSCHDXV * SDX † SDR Card address 0, bit offset 0 assumed. ...
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February 2002 Timing Characteristics (continued) Table 17. Serial Control Port Timing (See Figure 10.) Symbol Parameter tCSHLSET UPCS to UPCK Setup tCSLHHOD UPCS to UPCK Hold tUPDIST UPDI to UPCK Setup tUPDIHD UPDI to UPCK Hold tUPDODEL UPCK to UPDO ...
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Codec Chip Set Software Interface Table 18 lists the RAM data space for the DSP engine. Space for channels is allocated. The total T8531 RAM size is 4 Kwords, arranged Kbanks. Address bit ...
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February 2002 Software Interface (continued) Table 18. DSP Engine RAM Memory Map (continued) Address Range 0x04B5 Channel 8 ac filter coefficients 0x04C5 Channel 9 ac filter coefficients 0x04D5 Channel 10 ac filter coefficients 0x04E5 Channel 11 ac filter coefficients 0x04F5 ...
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Codec Chip Set Software Interface (continued) Table 19. T8531 Time-Slot Assignment Memory Map All registers can be written by the microprocessor interface. Address Range 0x1400 0x1401 0x1402 0x1403 0x1404 0x1405 0x1406 0x1407 0x1408 0x1409 0x140A 0x140B 0x140C 0x140D 0x140E 0x140F ...
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February 2002 Software Interface (continued) Table 21. T8531 Channel Register Memory Map for T8532 Device 0 All registers can be written by the microprocessor interface. Address Memory Range Contents 0x1500 Channel 0 powerup/powerdown register 0x1501 Channel 1 powerup/powerdown register 0x1502 ...
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Codec Chip Set Software Interface (continued) Table 24. Bit Map for T8532 Channel Control Register 1 at 0x1508—0x150F and 0x1548—0x154F 15 14—8 7 PWR Not used Table 25. T8532 Control Register 1: Transmit Gain Bit 7 Bit 6 TXGAIN2 TXGAIN1 ...
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February 2002 Software Interface (continued) Table 27. T8532 Control Register 1: Digital Loopback Bit 0 LPBK 0 1 Table 28. Bit Map for T8532 All Channel Test Register at 0x1510 and 0x1550 15—4 Not used Read out address Table 29. ...
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Codec Chip Set Software Interface (continued) Table 30. Bit Map for T8532 Channel Control Register 2 at 0x1518—0x151F and 0x1558—0x155F 15—8 7 Not used SUSEQ Notes: SUSEQ = 0: normal operation. SUSEQ = 1: start-up calibration sequence. Table 31. T8532 ...
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February 2002 Software Interface (continued) Table 33. Bits 15:8 of T8531 Board Control Word 1 at 0x1FFE Bit Number — — — — 1 — — — — — — — — 0 — ...
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Codec Chip Set Software Interface (continued) Table 35. Bits 15:9 of T8531 Board Control Word 2 at 0x1FFC Table 36. Bits 8:0 of T8531 Board Control Word 2 at 0x1FFC Bit Number BOF8 BOF7 BOF6 BOF5—3 Note: ...
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February 2002 Software Interface (continued) Table 41 shows the memory map for the DSP engine ROM. The ROM information is not accessible via the micro- processor. The total ROM size is 8 Kwords. Table 41. DSP Engine ROM Memory Map ...
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Codec Chip Set Applications Figure 11 shows a full line card implementation using the T8531/T8532 codec and the L7585 SLIC with inte- grated relays. One T8531 and two T8532 devices sup- port 16 SLIC devices (only one L7585 SLIC is ...
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February 2002 Applications (continued) Figure 12 shows the complete SLIC schematic for interfacing to the Agere L9215G short-loop, sine wave, ringing SLIC. All ac parameters are programmed by the codec. Note this codec differentiates itself in that no external com- ...
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Codec Chip Set Applications (continued) Figure 13 shows the complete SLIC schematic for interfacing to the Agere L9310G Line Interface and Line Access circuit. All ac parameters are programmed by the codec. Note this codec differentiates itself in that no ...
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February 2002 Applications (continued) Common Voltage Reference Every channel of the T8532 codec requires a 2.4 V ref- erence (VRTX) for operation. Some SLICs provide this reference for the codec. An external circuit is required for SLICs without the reference ...
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Codec Chip Set Outline Diagrams 64-Pin MQFP 1 16 DETAIL A 1.60 REF GAGE PLANE SEATING PLANE 46 17.20 0.25 14.00 0.20 PIN #1 IDENTIFIER ZONE DETAIL B 2.55/2.75 0.80 TYP 0.25 MAX 0.25 0.30/0.45 0.73/1.03 ...
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February 2002 Outline Diagrams (continued) 64-Pin TQFP 1 16 0.50 TYP 0.19/0.27 DETAIL B Agere Systems Inc. 12.00 0.20 10.00 0.20 PIN #1 IDENTIFIER ZONE DETAIL A DETAIL B 1.40 0.05/0.15 0.106/0.200 GAGE PLANE ...
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Codec Chip Set Ordering Information Device Code T-8531 - - - TL-DB 64-Pin TQFP, Dry pack tray T-8531 - - - TL-DT 64-Pin TQFP, Dry-bagged, Tape & Reel T-8532 - - - JL-DB 64-Pin MQFP, Dry pack tray T-8532 - ...