A3931 Allegro MicroSystems, Inc., A3931 Datasheet
A3931
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A3931 Summary of contents
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... JP) 3930-DS Preliminary Data Sheet Description The A3930 and A3931 are 3-phase brushless dc (BLDC) motor controllers for use with N-channel external power MOSFETs. They incorporate much of the circuitry required to design a cost effective three-phase motor drive system, and have been specifically designed for automotive applications ...
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... April 6, 2006 Automotive 3-Phase BLDC Controller combination on the Hall inputs. In this state, the A3930 indicates a logic fault, but the A3931 prepositions the motor in an unstable starting position suitable for start-up algorithms in microprocessor- driven “sensor-less” control systems. Both devices are supplied in a 48-pin LQFP with exposed thermal pad ...
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... A3930 and A3931 VBAT+ V5BD QV5 +5V Ref V5 CV5 MODE COAST BRAKE RESET DIR RDEAD PWM TACHO DIRO ESF Diagnostics and Protection –UVLO FF1 –TSD –Short to Supply –Short to Ground –Shorted Winding FF2 –Low Load Pad VDSTH Preliminary Data Sheet Subject to Change Without Notice ...
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... A3930 and A3931 ELECTRICAL CHARACTERISTICS Characteristics Supply and Reference 6 VBB Functional Operating Range VBB Quiescent Current V5 Quiescent Current VREG Output Voltage Bootstrap Diode Forward Voltage Bootstrap Diode Resistance Bootstrap Diode Current Limit Top-off Charge Pump Current Limit Cx Top-off Charge Pump Source Current ...
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... A3930 and A3931 ELECTRICAL CHARACTERISTICS Characteristics Logic Inputs and Outputs FFx Fault Output (Open Drain) FFx Fault Output Leakage Current 2 TACHO and DIRO Output High Voltage TACHO and DIRO Output Low Voltage Input Low Voltage Input High Voltage (Except RESET) RESET Input High Voltage ...
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... A3930 and A3931 ELECTRICAL CHARACTERISTICS Characteristics AC Common Mode Gain Common Mode Recovery Time Output Slew Rate Input Overload Recovery Time Current Limit Reference Comparator Input Offset Voltage Reference Input Clamp Voltage Comparator Blank Time REF Input Bias Current 2 RC Charge Current ...
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... A3930 and A3931 may require derating at maximum conditions, see Applications Information section THERMAL CHARACTERISTICS Characteristic Package Thermal Resistance Die-to-Exposed Pad Thermal Resis- tance *Additional thermal information available on Allegro Web site. Power Dissipation verus Ambient Temperature Preliminary Data Sheet Subject to Change Without Notice ...
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... These inputs are also filtered to further reduce the effects of switching noise. The HE inputs are pulled inside the A3930/A3931 through a high value (100 kΩ typical) resistor in series with a diode. This internal pull-up makes the HE input appear high if the Hall sensor signal is miss- ing, allowing detection input logic fault ...
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... Note that this is only available in the A3931. The A3930 will indicate a logic fault when all Hall inputs are driven low. The commutation truth table for these inputs is shown in table 3 ...
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... A3930 and A3931 greater than 20 kΩ. The upper limit for the resistor must be low enough to ensure that the input voltage reaches the input high threshold INR COAST An active-low input which turns all FETs off without disabling the supplies or control logic. This allows the external FETs and the motor to be protected in case of a short circuit ...
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... T When ESF = 0, under most conditions, although the fault flags, (μ FF1 and FF2, are still activated, the A3930/A3931will not disrupt normal operation and will therefore not protect the motor or the of 1.3 μs for BLANK drive circuit from damage imperative that the master control circuit or an external circuit take any necessary action when a fault occurs, to prevent damage to components ...
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... It is left to the user to turn off the device to prevent overtemperature damage to the chip and unpredictable device operation. • Logic Fault: Hall Invalid The A3930 and the A3931 differ slightly in how they handle error conditions on the Hall inputs, Hx. When all Hx are 1s, both devices evaluate this as an illegal code, and they pull both fault flags, FFx, low and coast the mo- tor ...
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... Device Both Both Both Both Both Both A3930 A3931 Both Both Both Both Both Both Both indicates “don’t care,” Z indicates high impedance state Table 3 ...
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... V5 must connected directly to V5BD and decoupled with at least a 220 nF capacitor between V5 and AGND. AGND The A3930/A3931 has a single ground connection at the AGND pin. The design ensures that only the operating current for the controller stage passes through this pin. The charge and discharge current for the external FETs does not pass though this pin ...
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... BOOTUV an undervoltage fault will be flagged, as shown in table 2. PWM Control The A3930 and A3931 have the flexibility to be used in many different motor control schemes. The internal PWM control can be used to provide fully integrated, closed-loop current control. Alternatively, current-mode or voltage-mode control are possible using external control circuits with either the DIR or the PWM input pins ...
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... Setting RESET = 1 and COAST = 0 overrides BRAKE and turns all motor bridge FETs off, coasting the motor. Driving a Full-Bridge. The A3930 and A3931 may be used to drive a full-bridge (for example, a brush dc motor load) by hard-wiring a single state for the Hall inputs and leaving the corresponding phase driver outputs floating ...
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... A3930 and A3931 Circuit Layout Because this is a switch-mode application, where rapid current changes are present, care must be taken during layout of the application PCB. The following points are provided as guidance for layout (refer to figure 3). Following all guidelines will not always be possible. However, each point should be carefully considered as part of any layout procedure ...
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... Controller Supply Ground Figure 3. Supply and Ground Connections Preliminary Data Sheet Subject to Change Without Notice April 6, 2006 Automotive 3-Phase BLDC Controller VBB VDRAIN GHC VREG GHB GHA A3930 A3931 GLA RC GLB VDSTH GLC RDEAD LSS AGND Optional components ...
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... A3930 and A3931 Gate Drive Outputs GHx VREG GLx 20 V LSS Supplies CP1 CP2 VDRAIN Logic Inputs COAST ESF 3 kΩ BRAKE DIR PWM MODE Monitor Threshold Input DS 1 kΩ 40 kΩ ...
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... A3930 and A3931 Terminal List Table Number Name 1 N.C. No connection 2 RESET Control for sleep mode 3 V5BD 5V regulator base drive regulator reference 5 FF2 Fault flag 2 6 FF1 Fault flag 1 7 TACHO Speed output 8 BRAKE Brake input 9 DIR Direction control input 10 H1 ...
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... A3930 and A3931 Package JP, 48-pin LQFP with Exposed Thermal Pad A B 9.20 .362 8.80 .346 7.20 .283 6.80 .268 48X 0.08 [.003] C 0.27 48X 0.17 0.08 [.003 Preliminary dimensions, for reference only (reference JEDEC MO-026 BBC) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions ...