PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 93

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
10.18 Transmit APS Interface
10.18.1
10.19 Transmit APS Overhead Processor
10.19.1
The POS-PHY Level 3 compliant interface accepts a write clock (TFCLK), a write enable
signal (TENB), the start of packet (TSOP) indication, the end of packet (TEOP) indication,
errored packet (TERR) indication and the parity bit (TPRTY) when data is written to the
transmit FIFO (using the rising edges of the TFCLK). The TADR[2:0] bus with TPA is used to
poll the channel FIFOs for fill status. As well, channels are selected using the TADR[2:0] and
falling edge of TENB. The The POS processor will not start transmitting a packet until a
programmable number of bytes for a single packet or the entire packet is in the FIFO. A packet
may be aborted by asserting the TERR signal at the end of the packet.
The interface also indicates FIFO overruns via a maskable interrupt and register bits. The TXFP
automatically transmits idle flag characters until sufficient data is available in the transmit FIFO
to start transmission.
The Transmit APS interface allows two S/UNI-8x155 devices to exchange SONET/SDH path
data streams. The transmit interface generates a SONET/SDH serial data stream with valid
section and path overheads. This allows performance monitoring and alarm generation to be
done in a similar manner to the serial line side interfaces.
The APS path information may be sourced from the receive side of a channel (RSOP/RLOP) or
from the transmit side of a channel (TPOP/TXFP/TXCP/TUL3).
APS Parallel to Serial Converter
The APS Parallel to Serial Converter (APISO) converts each transmit APS byte serial stream to
a bit serial stream. The transmit bit serial stream appears on the APSO[1:0]+/- PECL outputs.
The Transmit APS Overhead Processor (TAOP) provides frame pattern insertion (A1, A2),
scrambling and section BIP-8 (B1) insertion on the APS output stream. The processor is similar
to a Transmit Section Overhead processor (TSOP) except some features of the TSOP are not
supported.
Data Link Insert
The section DCC bytes (D1, D2 and D3) are used to imbed the transport alarm (section and/or
line alarms) status of the path data into the APS stream. When the section or line overheads of
the path data stream is in alarm condition (LOS, LOF, LAIS, LRDI or LOP), the DCC bytes are
set to all ones (0xFF). The DCC bytes are set to all zeros (0x00) when the section and line
overheads of the path data stream are not in alarm condition.
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
93