S1D13503 Epson Electronics America, Inc., S1D13503 Datasheet
S1D13503
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S1D13503 Summary of contents
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... S1D13503 Graphics LCD Controller S1D13503 TECHNICAL MANUAL Issue Date: 01/01/30 Document Number: X18A-Q-001-07 Copyright © 1997, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page ii S1D13503 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Issue Date: 01/01/30 ...
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... Tel: 089-14005-0 Fax: 089-14005-110 Page iii Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 S1D13503 ...
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... Page iv S1D13503 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Issue Date: 01/01/30 ...
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... Epson Research and Development Vancouver Design Center INTRODUCTION S1D13503 Graphics LCD Controller Data Sheet SPECIFICATION S1D13503 Hardware Functional Specification PROGRAMMER’S REFERENCE S1D13503 Programming Notes and Examples UTILITIES 13503SHOW.EXE Display Utility 13503VIRT.EXE Display Utility 13503BIOS.COM Display Utility 13503MODE.EXE Display Utility 13503PD.EXE Power Down Utility 13503READ ...
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... Page vi S1D13503 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Issue Date: 01/01/30 ...
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... S1D13503 GRAPHICS LCD CONTROLLER DESCRIPTION The S1D13503 is a dot matrix graphic LCD controller supporting resolutions up to 1024x1024 capable of displaying a maximum of 256 simultaneous colors out of a possible 4096 or 16 gray shades. Design flexibility allows the S1D13503 to interface to either an MC68000 family microprocessor or an 8/16-bit MPU/bus with minimum external logic ...
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... S1D13503 SYSTEM BLOCK DIAGRAM Control CPU Clock CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS: • S1D13503 Technical Manual • S5U13503 Evaluation Boards • CPU Independent Software Utilities Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan ...
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... S1D13503 Dot Matrix Graphics Color LCD Controller Hardware Functional Specification Document Number: X18A-A-001-08 Copyright © 1997, 2001Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13503 X18A-A-001-08 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/01/29 ...
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... PINOUT DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . 26 6 D.C. CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 A.C. CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 Bus Interface Timing 7.1.1 MC68000 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1.2 Non-MC68000, MPU/Bus With READY (or WAIT#) Signal . . . . . . . . . . . . . . . 33 7.2 Clock Input Requirements 7.2.1 Recommended Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Hardware Functional Specification Issue Date: 01/01/29 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 3 S1D13503 X18A-A-001-08 ...
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... Display Memory Interface 9.2.2 16-bit Display Memory Interface 9.3 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.3.1 For single panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.3.2 For dual panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.4 Memory Size Calculation 9.5 Memory Size Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10 MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 S1D13503 X18A-A-001- Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/01/29 ...
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... Display Memory Interface SRAM Access Time Table 9-3: Memory Size Requirement: Number of Horizontal Pixels = 640 . . . . . . . . . . . . . . . . . . . . 85 Table 9-4: Memory Size Requirement: Number of Horizontal Pixels = 480 . . . . . . . . . . . . . . . . . . . . 86 Table 9-5: Memory Size Requirement: Number of Horizontal Pixels = 320 . . . . . . . . . . . . . . . . . . . . 86 Hardware Functional Specification Issue Date: 01/01/29 List of Tables Page 5 S1D13503 X18A-A-001-08 ...
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... Page 6 S1D13503 X18A-A-001-08 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/01/29 ...
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... Figure 3: 16-Bit Mode, Example: i8086 (maximum mode Figure 4: 8-Bit Mode (ISA Figure 5: 16-Bit Mode (ISA Figure 6: Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 7: S1D13503 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 8: S1D13503 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 9: S1D13503 Pad Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 10: IOW# Timing (MC68000 .29 Figure 11: IOR# Timing (MC68000 .30 Figure 12: MEMW# Timing (MC68000) ...
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... Figure 47: 16-Bit Mode - 16K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 48: 16-Bit Mode - 64K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 49: 16-Bit Mode - 128K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 50: Mechanical Drawing QFP5-100-S2 (S1D13503 Figure 51: Mechanical Drawing QFP15-100-STD (S1D13503 S1D13503 X18A-A-001-08 Epson Research and Development Vancouver Design Center Hardware Functional Specification ...
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... S1D13502 within the same package types (e.g. the 13503D0A is pin compatible with the 13502; the 13503 is pin compatible with the 13502). The S1D13503 is capable of displaying a maximum of 16 levels of gray shade or 256 simultaneous colors. In gray shade modes, a 16x4 Look-Up Table is provided to allow remapping of the 16 possible gray shades displayed on the LCD panel. ...
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... AUX[0A]) • virtual display mode (see AUX[0D]) Note 256 color display mode support requires a 16-bit display memory interface S1D13503 X18A-A-001-08 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/01/29 ...
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... See Section 9.5 on page 85 for complete details 2.5 Power Management • two software power-save modes • low power consumption • panel power control switch (see AUX[01] bit 4) Hardware Functional Specification Issue Date: 01/01/29 Page 11 S1D13503 X18A-A-001-08 ...
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... Page 12 3 TYPICAL SYSTEM BLOCK DIAGRAMS The following figures show typical system implementations of the S1D13503. All of the following block diagrams are shown without SRAM or LCD display. Refer to the interface specific Application Notes for complete details. 3.1 16-Bit MC68000 MPU MC68000 A20 to A23 ...
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... T OE Transceiver (example implementation only - actual may vary) Page 13 S1D13503 MEMCS# IOCS# AB0 to AB15 DB0 to DB7 READY MEMW# MEMR# IOR# IOW# RESET S1D13503 MEMR# MEMW# IOR# IOW# AB16 to AB19 AB0 to AB15 BHE# MEMCS# IOCS# DB0 to DB15 RESET READY S1D13503 X18A-A-001-08 ...
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... Epson Research and Development Vancouver Design Center S1D13503 MEMCS# MEMW# MEMR# READY DB0 to DB7 AB0 to AB19 IOCS# IOW# IOR# RESET SA through SA9 S1D13503 MEMCS# MEMW# MEMR# READY DB0 to DB15 AB0 to AB19 IOCS# IOW# IOR# BHE# RESET SA through SA9 Hardware Functional Specification ...
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... Control Registers Port Decoder Sequence Controller Memory Decoder Data Bus Address Generator MPU/CRT Selector Timing Generator Power Save Oscillator Figure 6: Internal Block Diagram Lookup LCD Table Panel Interface Display Data Formatter SRAM Interface X18A-A-001-08 Page 15 LCDENB UD[3:0] LD[3:0] LP, YD, XSCL, WF(XSCL2) S1D13503 ...
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... MCLK = input clock - MCLK = 1/2 input clock - MCLK = 1/4 input clock. Pixel clock = input clock = f OSC. 3.5.13 SRAM Interface The SRAM Interface generates the necessary signals to interface to the Display Memory (SRAM). S1D13503 X18A-A-001-08 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/01/29 ...
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... Package type: 100 pin surface mount QFP5-S2. Note * Pin all display modes except format 1 for 8-bit single color panel. * Pin 80 = XSCL2 in format 1 for 8-bit single color panel. Hardware Functional Specification Issue Date: 01/01/29 S1D13503F00A Figure 7: S1D13503F00A Pinout Diagram Page 17 50 VD6 49 VD5 48 ...
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... Package type: 100 pin surface mount QFP15-STD. Note * Pin all display modes except format 1 for 8-bit single color panel. * Pin 77 = XSCL2 in format 1 for 8-bit single color panel. S1D13503 X18A-A-001-08 S1D13503F01A Figure 8: S1D13503F01A Pinout Diagram Epson Research and Development Vancouver Design Center ...
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... Pad all display modes except format 1 for 8-bit single color panel. * Pad 97 = XSCL2 in format 1 for 8-bit single color panel. Hardware Functional Specification Issue Date: 01/01/ S1D13503D00A 10 20 5.030 mm x 5.030 mm 0.400 mm 0.090 mm x 0.090 mm 0.126 mm (Min.) Figure 9: S1D13503D00A Pad Diagram Page 19 Dummy Pad 70 VD7 VD6 VD5 60 VD4 VD3 VD2 VD1 VD0 ...
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... AB13 1.388 28 AB14 1.535 29 AB15 1.685 30 AB16 1.840 31 --- 2.000 32 AB17 2.165 33 AB18 2.390 34 --- 2.390 35 --- 2.390 36 AB19 2.390 S1D13503 X18A-A-001-08 Table 4-1: PAD Coordinates Pad Center Pad Coordinate No. Name X Y -2.390 37 RESET -2.390 38 -2.390 39 -2.390 40 -2.390 41 -2.390 42 -2.390 43 -2.390 44 -2.390 45 -2.390 46 -2 ...
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... DB0 -2.390 -0.703 DB1 -2.390 -0.835 --- -2.390 -0.969 DB2 -2.390 -1.106 DB3 -2.390 -1.246 DB4 -2.390 -1.388 DB5 -2.390 -1.535 DB6 -2.390 -1.685 --- -2.390 -1.840 --- -2.390 -2.000 DB7 -2.390 -2.165 2.390 2.390 -2.390 -2.390 X18A-A-001-08 Page 21 S1D13503 ...
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... AB1 AB19 BHE IOCS S1D13503 X18A-A-001-08 = 5.0V, see Table 6-3, “Input Specifications,” on page 27) DD Table 5-1: Bus Interface D00A Driver Description Pad # 118- 119, 121- These pins are connected to the system data bus. In 8-bit bus TS2 125, ...
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... TS3 needed. READY is placed in a high impedance (Hi-Z) state after the transfer is completed. 37 TTLS Active high input to force all signals to their inactive states MC68000 MPU interface MC68000 MPU interface. DD S1D13503 X18A-A-001-08 Page 23 ...
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... VOE 102 S1D13503 X18A-A-001-08 Table 5-2: Display Memory Interface Driver Description These pins are connected to the display memory data bus. For 16- bit interface, VD0-VD7 are connected to the display memory data bus of even byte addresses and VD8-VD15 are connected to the display memory data bus of odd byte addresses ...
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... This pin, along with OSC1, is the 2-terminal crystal interface when using a 2-terminal crystal as the clock input external 116 * oscillator is used as a clock source this pin should be left unconnected. Table 5-5: Power Supply F01A Pin # D00A Pad # 50, 100 Page 25 Driver Description P Voltage supply P Voltage ground S1D13503 X18A-A-001-08 ...
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... Page 26 5.2 Summary of Configuration Options The S1D13503 requires some configuration information on power-up. This information is provided through the SRAM data lines VD[0...15]. The state of these pins are read on the falling edge of RESET and used to configure the following options: Table 5-6: Summary of Power On / Reset Options Pin Name ...
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... Table 6-3: Input Specifications Condition Units Min Typ Max 2.7 3.0/3.3/5.0 5 4.5/5.0/11 - 13.5/16.5/55 Min Typ Max 0.8 0.4 0.3 2.0 1.3 1.2 2.4 1.4 1.3 0.6 0.5 0.4 0.1 0.1 0 S1D13503 X18A-A-001-08 Page 27 Units Units ...
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... High Level Output Voltage Type 1 - TS1D2, CO1 V (3.0V) OH Type 2 - TS2, CO2 Type 3 - TS3, CO3, CO3S I Output Leakage Current OZ C Output Pin Capacitance OUT C Bidirectional Pin Capacitance BID S1D13503 X18A-A-001-08 Table 6-3: Input Specifications (Continued) Condition f =1 MHz 5. ...
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... VALID t4 Hi-Z t5 Hi-Z Figure 10: IOW# Timing (MC68000) Table 7-1: IOW# Timing (MC68000) Parameter Min Max Min Max - Hi Hi-Z VALID 3V/3.3V 5V Units X18A-A-001-08 Page 29 S1D13503 ...
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... AS# falling edge to DTACK# falling edge t4 AS# rising edge to DTACK# hi-z delay t5 AS# falling edge to DB[15:0] valid t6 DB[15:0] hold from AS# rising edge t7 AS# rising edge to DB[15:0] hi-z delay S1D13503 X18A-A-001-08 VALID t3 t5 VALID Figure 11: IOR# Timing (MC68000) Table 7-2: IOR# Timing (MC68000) Parameter Min Max Min Max ...
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... Table 7-3: MEMW# Timing (MC68000) Parameter Min , or 4/f depending on which display mode the chip is in. (see section 9.2 and OSC OSC t2 t4 Hi-Z t6 Hi-Z VALID 3V/3.3V 5V Max Min Max Units 3.5 * 3.5 * MCLK MCLK MCLK MCLK ns -40 - X18A-A-001-08 Page 31 S1D13503 ...
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... DTACK# falling edge to DB[15:0] valid t6 DB[15:0] hold from AS# rising edge t7 AS# rising edge to DB[15:0] hi-z delay Where MCLK period = 1 2/f OSC 9.3) S1D13503 X18A-A-001-08 VALID t3 t5 Figure 13: MEMR# Timing (MC68000) Table 7-4: MEMR# Timing (MC68000) Parameter Min , or 4/f depending on which display mode the chip is in. (see section 9.2 and ...
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... DB[15:0] setup to IOW# rising edge t4 DB[15:0] hold from IOW# rising edge t5 Pulse width of IOW# Hardware Functional Specification Issue Date: 01/01/29 VALID t5 t3 Hi-Z VALID Figure 14: IOW# Timing (Non-MC68000) Parameter Min Max Min Max Hi-Z 3V/3.3V 5V Units X18A-A-001-08 Page 33 S1D13503 ...
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... AB[9:0], BHE# and IOCS# hold from IOR# rising edge t3 IOR# falling edge to DB[15:0] valid t4 DB[15:0] hold from IOR# rising edge t5 IOR# rising edge to DB[15:0] hi-z delay S1D13503 X18A-A-001-08 VALID t3 VALID Figure 15: IOR# Timing (Non-MC68000) Table 7-6: IOR# Timing (Non-MC68000) Parameter Epson Research and Development Vancouver Design Center ...
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... Figure 16: MEMW# Timing (Non-MC68000) Table 7-7: MEMW# Timing (Non-MC68000) Parameter Min , or 4/f depending on which display mode the chip is in. (see section 9.2 and OSC OSC t2 Hi-Z t5 Hi-Z 3V/3.3V 5V Max Min Max Units MCLK MCLK ns -40 - 3.5* 3.5* MCLK MCLK X18A-A-001-08 Page 35 S1D13503 ...
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... READY rising edge to DB[15:0] valid t5 DB[15:0] hold from MEMR# rising edge t6 MEMR# rising edge to DB[15:0] hi-z delay t7 READY negated pulse width Where MCLK period = 1 2/f OSC 9.3.) S1D13503 X18A-A-001-08 VALID t3 t7 Hi-Z Hi-Z t4 Figure 17: MEMR# Timing (Non-MC68000) Table 7-8: MEMR# Timing (Non-MC68000) Parameter , or 4/f depending on which display mode the chip is in. (See section 9.2 and ...
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... Input Clock Fall Time (10 Input Clock Rise Time (10% - 90%) r Hardware Functional Specification Issue Date: 01/01/ PWH PWL OSC Figure 18: Clock Input Requirements Table 7-9: Clock Input Requirements Min 40 40% 40% Typ Max Units ns 60% T OSC 60% T OSC S1D13503 X18A-A-001-08 Page 37 ...
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... The nominal frequency must be calculated based on the formulas found in Frame Rate Calculation on page 84. The crystal oscillator must be “fundamental mode” and have the following recommended RC load values ± 6 The figure below demonstrates both a crystal interface and an oscillator interface to the S1D13503. Crystal Interface 92 R S1D13503 93 S1D13503 X18A-A-001-08 ...
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... Figure 20: Write Data to Display Memory 3V/3.3V Min Max MCLK - MCLK - 15 MCLK - 4/f depending on which display mode the chip is in. (See section 9.2 and OSC OSC Page 39 Hi-Z INPUT 5V Min Max Units MCLK - MCLK - 10 ns MCLK - S1D13503 X18A-A-001-08 ...
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... VD[15:0] Table 7-11: Read Data From Display Memory Symbol Parameter t1 Address cycle time t2 VA[15:0], VCS0# and VCS1# access time t3 VD[15:0] hold time Where MCLK period = 1 2/f OSC 9.3.) S1D13503 X18A-A-001-08 VALID INPUT INPUT Figure 21: Read Data From Display Memory 3V/3.3V Min MCLK - 4/f depending on which display mode the chip is in. (See section 9.2 and ...
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... Vancouver Design Center 7.4 LCD Interface 7.4.1 LCD Interface Timing - 4-Bit Single, 8-Bit Single/Dual Monochrome Panels S1D13503 outputs S1D13503 outputs (AUX[01] bit XSCL UD[3:0] LD[3:0] S1D13503 outputs (AUX[01] bit XSCL UD[3:0] 80 LD[3:0] Figure 22: LCD Interface Timing - Monochrome Panel Hardware Functional Specification Issue Date: 01/01/ t6a ...
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... XSCL high width (AUX[03] bit t10 XSCL low width (AUX[03] bit t10 XSCL low width (AUX[03] bit UD[3:0], LD[3:0] setup to XSCL falling edge (AUX[03] bit 2 t11 = 0) S1D13503 X18A-A-001-08 Epson Research and Development Vancouver Design Center 4-Bit Single 8-Bit Single/Dual Min Max ...
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... HNDP = horizontal non-display period in units -10 ns for 5V operation for 3.0V and 3.3V operation. Hardware Functional Specification Issue Date: 01/01/ 10** OSC OSC OSC OSC , OSC (see Section 9.3 on page 84 for details). OSC Page 10** ns OSC OSC OSC OSC S1D13503 X18A-A-001-08 ...
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... Page 44 7.4.2 LCD Interface Timing - 4-Bit Single Color Panel XSCL UD Figure 23: LCD Interface Timing - 4-Bit Single Color Panel S1D13503 X18A-A-001- t13 t9 t10 t11 t12 1 2 Epson Research and Development Vancouver Design Center Hardware Functional Specification ...
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... Min Typ HT + HNDP - 10 13t - 10 OSC OSC 0 19t - 5 OSC 20t - 5 OSC 14t - 5 OSC OSC 0. OSC 0. OSC 0.5t - 10** OSC 0. OSC 13. OSC , OSC (see Section 9.3 on page 84 for details). OSC - 24. OSC Page 45 Max Units S1D13503 X18A-A-001-08 ...
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... Page 46 7.4.3 LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels XSCL UD/LD Figure 24: LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels S1D13503 X18A-A-001- t13 t9 t10 t11 t12 1 2 Epson Research and Development ...
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... OSC OSC 0 19. OSC 20t - 5 OSC 52t - 5 OSC 14. OSC 2. OSC OSC 1. OSC 1.5t - 10** OSC OSC 13. OSC , OSC (see Section 9.3 on page 84 for details). OSC - 24. OSC Page 47 Typ Max Units S1D13503 X18A-A-001-08 ...
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... Page 48 7.4.4 LCD Interface Timing - 16-Bit Single/Dual Color Panels XSCL UD/LD Figure 25: LCD Interface Timing - 16-Bit Single/Dual Color Panels S1D13503 X18A-A-001- t13 t9 t10 t14 t11 t12 1 2 Epson Research and Development Vancouver Design Center t1 t15 3 4 Hardware Functional Specification ...
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... OSC 17t - 5 OSC OSC OSC OSC 1.5t - 10** OSC OSC 15t - 10 OSC 1. OSC 0. OSC , OSC (see Section 9.3 on page 84 for details). OSC - 24. OSC Page 49 Typ Max Units S1D13503 X18A-A-001-08 ...
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... Page 50 7.4.5 LCD Interface Timing - 8-Bit Single Color Panels Format t7a t7b LP XSCL2 (WF) XSCL UD/LD Figure 26: LCD Interface Timing - 8-Bit Single Color Panels Format 1 S1D13503 X18A-A-001-08 t3 t6a t6b t8b t14b t11b t8a t14a t12b t12a t13b 1 2 Epson Research and Development ...
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... OSC OSC OSC OSC 1.5t - 10** OSC 1.5t - 10** OSC OSC OSC 16t - 10 OSC 13. OSC , OSC (see Section 9.3 on page 84 for details). OSC - 24. OSC Page 51 Max Units S1D13503 X18A-A-001-08 ...
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... Page 52 7.4.6 LCD Interface Options UD[3:0] LINE1 LP WF XSCL UD3 UD2 UD1 UD0 Example Timing for a 320x240 single panel S1D13503 X18A-A-001- 240 PULSES LINE2 LINE3 LINE4 LINE239 LINE240 XSCL: 80 CLOCK PERIODS 1-1 1-5 1-2 1-6 1-3 1-7 1-4 1-8 Figure 27: 4-Bit Single Monochrome Panel Timing Epson Research and Development ...
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... Example timing for a 640x480 panel Hardware Functional Specification Issue Date: 01/01/ 480 PULSES LINE1 LINE2 LINE3 LINE4 XSCL:80 CLOCK PERIODS 1-1 1-9 1-2 1-10 1-3 1-11 1-4 1-12 1-5 1-13 1-6 1-14 1-7 1-15 1-8 1-16 Figure 28: 8-Bit Single Monochrome Panel Timing LP: 4 PULSES LINE479 LINE480 LINE1 1-633 1-634 1-635 1-636 1-637 1-638 1-639 1-640 X18A-A-001-08 Page 53 LINE2 S1D13503 ...
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... Page UD[3:0], LD[3: XSCL UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 Example timing for a 640x480 panel S1D13503 X18A-A-001- 240 PULSES LINE1/241 LINE2/242 LINE3/243 LINE4/244 XSCL: 160 CLOCK PERIODS 1-1 1-5 1-2 1-6 1-3 1-7 1-4 1-8 241-1 241-5 241-2 241-6 241-3 241-7 241-4 241-8 Figure 29: 8-Bit Dual Monochrome Panel Timing ...
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... UD1 UD0 Example timing for a 320x240 panel Hardware Functional Specification Issue Date: 01/01/ 240 PULSES LINE2 LINE3 LINE4 LINE239 LINE240 XSCL: 240 CLOCK PERIODS 1-G2 1-B3 1-G1 1-B2 1-R4 1-B1 1-R3 1-G4 1-R2 1-G3 1-B4 Figure 30: 4-Bit Single Color Panel Timing Page 55 LP: 4 PULSES LINE1 LINE2 1-B319 1-R320 1-G320 1-B320 S1D13503 X18A-A-001-08 ...
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... UD0 1-B3 LD3 1-G4 LD2 1-R5 LD1 1-B5 LD0 Example timing for a 640x480 panel Figure 31: 8-Bit Single Color Panel Timing - Format 1 : AUX[03] Bit and AUX[01] Bit S1D13503 X18A-A-001-08 LP: 480 PULSES LINE2 LINE3 LINE4 LINE479 XSCL2: 120 CLOCK PERIODS XSCL: 120 CLOCK PERIODS 1-G1 1-G6 ...
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... Figure 32: 8-Bit Single Color Panel Timing - Format 2 : AUX[03] Bit and AUX[01] Bit Hardware Functional Specification Issue Date: 01/01/ 240 PULSES LINE2 LINE3 LINE4 LINE239 XSCL: 120 CLOCK PERIODS 1-B3 1-G6 1-R4 1-B6 1-G4 1-R7 1-B4 1-G7 1-R5 1-B7 1-G5 1-R8 1-B5 1-G8 1-R6 1-B8 LP: 4 PULSES LINE240 LINE1 LINE2 1-G318 1-B318 1-R319 1-G319 1-B319 1-R320 1-G320 1-B320 S1D13503 X18A-A-001-08 Page 57 ...
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... LD3 241-G1 241-B2 LD2 241-B1 241-R3 LD1 241-R2 241-G3 LD0 Example timing for a 640x480 panel FROM S1D13503 Figure 34: External Circuit Required for 16-Bit Panel S1D13503 X18A-A-001-08 LP: 240 PULSES LINE2 LINE3 LINE4 LINE239 LINE242 LINE243 LINE244 LINE479 XSCL: 480 CLOCK PERIODS 1-G2 1-B3 1-B2 ...
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... Page 59 LP: 4 PULSES LINE480 LINE1 LINE2 1-B635 1-G638 1-G636 1-R639 1-R637 1-B639 1-B637 1-G640 1-R636 1-B638 1-B636 1-G639 1-G637 1-R640 1-R638 1-B640 1-B635 1-G636 1-R637 1-B637 1-G638 1-R639 1-B 639 1-G640 1-R636 1-B636 1-G637 1-R638 1-B638 1-G639 1-R640 1-B640 S1D13503 X18A-A-001-08 ...
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... UD4 UD3 UD2 UD1 UD0 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 Example timing for a 640x480 panel Figure 36: 16-Bit Dual Color Panel Timing with External Circuit S1D13503 X18A-A-001- 240 PULSES LINE1/241 LINE2/242 LINE3/243 LINE4/244 LINE239/479 LINE240/480 XSCL: 240 CLOCKS 1-R1 1-G2 1-B3 1-G1 1-B2 1-R4 ...
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... Epson Research and Development Vancouver Design Center 8 HARDWARE REGISTER INTERFACE The S1D13503 is configured and controlled via 16 internal 8-bit registers. There are two ways to map these registers into the system I/O space. 1. Direct-mapping: Absolute I/O address = system address lines AB[3:0] + base I/O mapped address (where base I/O address is selected by VD7-VD12, see Table 5-6) This scheme requires 16 sequential I/O addresses starting from the I/O mapped base address selected by VD7-VD12 (see Table 5-6) ...
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... This bit is ignored when either black-and-white (BW) or 256 color mode is selected (AUX[03] bit 2 = 1). This bit goes low on RESET. Table 8-1: Gray Shade/Color Mode Selection Display Modes 256 Colors 16 Colors 4 Colors 16 Grays 4 Grays BW S1D13503 X18A-A-001-08 Gray Shade / LCDE Color Gray Shade/ BW/ Color Mode Color 256 Colors AUX[03] bit 1 ...
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... LCD data width (with external circuit 8-bit LCD data width - format 2 Line Byte Line Byte Line Byte Count Bit 4 Count Bit 3 Count Bit 2 BitsPerPixel = -------------------------------------------------------------- MemoryInterfaceWidth 4BitsPerPixel = ------------------------------------ - 16Bits Function Line Byte Line Byte Count Bit 1 Count Bit 0 HorizontalResolution – 1 640 1 – = 159 X18A-A-001-08 Page 63 S1D13503 ...
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... There is no effect on changing this bit in BW and color modes display mode, the Look-Up Table is always bypassed and in color display mode the Look-Up Table cannot be bypassed. The LUT Bypass bit goes low on RESET. S1D13503 X18A-A-001-08 Maximum Value of ...
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... Bits 8 and 9 are located in the following register (AUX[05]). Hardware Functional Specification Issue Date: 01/01/29 Total Disp. Total Disp. Total Disp. Line Count Line Count Line Count Bit 4 Bit 3 Bit 2 = NumberOfDisplayLines 1 NumberOfDisplayLines = --------------------------------------------------------------- 2 Page 65 Total Disp. Total Disp. Line Count Line Count Bit 1 Bit 0 – – 1 S1D13503 X18A-A-001-08 ...
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... Note The absolute address into display memory is determined by the Memory Mapping Address which is set by VD13 - VD15 (see Table 5-6, “Summary of Power On / Re- set Options,” on page 26). S1D13503 X18A-A-001-08 WF Count WF Count WF Count ...
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... Display Display Display Start Addr Start Addr Start Addr Bit 12 Bit 11 Bit 10 ImageVerticalResolution MemoryInterfaceWidth ---------------------------------------------------------------- 2 8 Page 67 Screen 2 Screen 2 Display Display Start Addr Start Addr Bit 1 Bit 0 Screen 2 Screen 2 Display Display Start Addr Start Addr Bit 9 Bit 8 BytesPerPixel + Screen1DisplayStartAddress S1D13503 X18A-A-001-08 ...
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... AUX[09]). Two different images can be displayed when using a dual panel configuration by changing the screen 2 dis- play start address. However, by using this method screen 2 is limited to the lower half of the display. This register is ignored in dual panel mode. S1D13503 X18A-A-001-08 Screen 1 Screen 1 ...
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... Display Period Period Period Bit 4 Bit 3 Bit 2 Addr Pitch Addr Pitch Addr Pitch Adjustment Adjustment Adjustment Bit 4 Bit 3 Bit 2 Page 69 Horizontal Horizontal Non- Non- Display Display Period Period Bit 1 Bit 0 Addr Pitch Addr Pitch Adjustment Adjustment Bit 1 Bit 0 S1D13503 X18A-A-001-08 ...
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... ID Bit / RGB Index Bits [1:0] These bits have dual purpose; ID Bits: After power on or hardware reset, these bits can be read to identify the S1D13503. These same bits are used to identify the pin compatible S1D13502 and would only be used in system implementations where common software is being used. As these bits are R/W they must be read before being written in order to be used as ID bits ...
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... Look-Up Table position one and display the 4-bit gray shade corresponding to the value programmed into that location. Hardware Functional Specification Issue Date: 01/01/29 Blue Bank Palette Data Palette Data Bit 0 Bit 3 Bit 2 Page 71 Palette Data Palette Data Bit 1 Bit 0 S1D13503 X18A-A-001-08 ...
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... Note: the above depiction is intended to show the display data output path only. The CPU R/W access to the individual Look-Up Tables is not affected by the various ‘banking’ configurations. Figure 37: 4-Level Gray-Shade Mode Look-Up Table Architecture S1D13503 X18A-A-001-08 4-bit wide Palette GREEN ...
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... P3, P2, P1 msb lsb Figure 38: 16-Level Gray-Shade Mode Look-Up Table Architecture Note The Look-Up Table is bypassed in black-and-white display mode Hardware Functional Specification Issue Date: 01/01/29 Green Look-Up Table 16x4 4-bit Look-Up Table data output Page 73 S1D13503 X18A-A-001-08 ...
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... Color Mode 2-bit pixel data Red Bank Select bits [1:0] (Aux[0F] bits [7:6]) Green Bank Select bits [1:0] (Aux[0E] bits [7:6]) Blue Bank Select bits [1:0] (Aux[0F] bits [5:4]) Figure 39: 4-Level Color Mode Look-Up Table Architecture S1D13503 X18A-A-001-08 RED Look-Up Table Bank Bank 1 ...
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... Look-Up Table data output Green Look-Up Table 16x4 4-bit ‘GREEN’ Look-Up Table data output Blue Look-Up Table 16x4 4-bit ‘BLUE’ Look-Up Table data output Page 75 S1D13503 X18A-A-001-08 ...
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... G1, G0) Green Bank Select bit (Aux[0E] bit 6) 2-bit pixel data (B1, B0) Blue Bank Select bits [1:0] (Aux[0F] bits [5:4]) Figure 41: 256-Level Color Mode Look-Up Table Architecture S1D13503 X18A-A-001-08 Epson Research and Development Red Look-Up Table Bank 4-bit ‘ ...
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... Reserved 8.3.1 Power Save Mode 1 Power Save Mode 1 has two states. Initially when set, the S1D13503 enters State valid memory cycle is detected within clocks (input clock frequency dependent), the chip will enter State 2. The number of clocks of inactivity before entering State 2 is dependent on the display memory interface and the number of Gray shades. ...
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... Active WF/XSCL2 (Note 2) AB[19:0], DB[15:0] Active IOR#, IOW# Active MEMR#, MEMW# Active RESET Active Note 1. Internal Register AUX[03], bit Internal Register AUX[03], bit S1D13503 X18A-A-001-08 Power Save Mode (PSM) Normal PSM1 (Active) State 1 State 2 Yes No No Yes Yes Yes Yes ...
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... Mode Hardware Functional Specification Issue Date: 01/01/29 VD0-7 VWE# WE# 8Kx8 S1D13503 CS# VCS0# n/c VCS1# VA0-12 Figure 42: 8-Bit Mode - 8K bytes SRAM VD0-7 VWE# WE# 8Kx8 S1D13503 CS# VCS0# VCS1# VA0-12 Figure 43: 8-Bit Mode - 16K bytes SRAM (Requires AUX[01] bit Page 79 WE# 8Kx8 CS# S1D13503 X18A-A-001-08 ...
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... S1D13503 CS# VCS0# VCS1# n/c VA0-14 Figure 44: 8-Bit Mode - 32K bytes SRAM (Requires AUX[01] bit VD0-7 VWE# WE# 8K/32Kx8 S1D13503 CS# VCS0# VCS1# VA0-14 Figure 45: 8-Bit Mode - 40K bytes SRAM Epson Research and Development Vancouver Design Center WE# 32K/8Kx8 CS# Hardware Functional Specification Issue Date: 01/01/29 ...
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... Hardware Functional Specification Issue Date: 01/01/29 VD0-7 VWE# WE# 32Kx8 S1D13503 CS# VCS0# VCS1# VA0-14 Figure 46: 8-Bit Mode - 64K bytes SRAM (Requires AUX[01] bit VD0-7 VWE# VCS0# VA0-12 VCS1# VD8-15 Figure 47: 16-Bit Mode - 16K bytes SRAM WE# 32Kx8 CS# WE# 8Kx8 CS# CS# 8Kx8 WE# S1D13503 X18A-A-001-08 Page 81 ...
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... Page 82 S1D13503 S1D13503 S1D13503 X18A-A-001-08 VD0-7 VWE# VCS0# VA0-14 VCS1# VD8-15 Figure 48: 16-Bit Mode - 64K bytes SRAM VWE# WE# VCS0# LB# VCS1# UB# VA0-15 A0-15 VD0-7 I/O 1-8 VD8-15 I/O 9-16 Figure 49: 16-Bit Mode - 128K bytes SRAM Epson Research and Development Vancouver Design Center WE# 32Kx8 CS# CS# 32Kx8 WE# ...
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... OSC - 40ns Access time < OSC Access time < 40ns Access time < OSC Access time < 40ns Access time < OSC Page 25ns OSC - 25ns OSC - 25ns OSC 5V - 25ns OSC - 25ns OSC - 25ns OSC - 25ns OSC S1D13503 X18A-A-001-08 ...
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... DHNDP = 16 pixels per panel in gray shade display modes, and DHNDP = 32 pixels per panel in BW display mode and in color display modes. Where PHNDP is Programmable Horizontal Non-Display Period in term of pixels : PHNDP = 0 pixels when AUX[0C and AUX 0C PHNDP = ---------------------------------------------------------------------------------------------------------------- - S1D13503 X18A-A-001- osc = ------------------------------------------------------------------------------------------------------------------------------------------------------------------- - HorizontalPixels PHNDP ...
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... Memory more than 128KB cannot be supported by S1D13503. (2) Memory more than 64KB can only be supported through 16-bit display memory interface. (3) 256 color mode must use 16-bit display memory interface byte = 1024 bytes Hardware Functional Specification Issue Date: 01/01/29 ...
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... Memory more than 128KB cannot be supported by S1D13503. (2) Memory more than 64KB can only be supported through 16-bit display memory interface. (3) 256 color mode must use 16-bit display memory interface byte = 1024 bytes S1D13503 X18A-A-001-08 ...
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... Epson Research and Development Vancouver Design Center 10 MECHANICAL DATA QFP5-100PIN-S2 (S1D13503) 81 100 All dimensions in mm Figure 50: Mechanical Drawing QFP5-100-S2 (S1D13503F00A) Hardware Functional Specification Issue Date: 01/01/29 ± 0.04 23.2 ± 0.1 20 Index ± 0.1 ± 0.1 1 0.65 0. 0~12° ± 0.1 0.8 1.6 X18A-A-001-08 Page 87 S1D13503 ...
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... Page 88 QFP15-100PIN-STD (S1D13503) All dimensions in mm Figure 51: Mechanical Drawing QFP15-100-STD (S1D13503F01A) S1D13503 X18A-A-001-08 ± 0.4 16.0 ± 0.1 14 Index 100 1 ± 0.1 0.168 0.5 ± 0.2 0.5 1 Epson Research and Development Vancouver Design Center 0~12° Hardware Functional Specification Issue Date: 01/01/29 ...
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... S1D13503 Dot Matrix Graphics LCD Controller Programming Notes and Examples Document Number: X18A-G-002-06 Copyright © 1996, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13503 X18A-G-002-06 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/01/30 ...
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... Epson Research and Development Vancouver Design Center 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 INITIALIZING THE S1D13503 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 GRAY SHADES / COLORS AND LOOK-UP TABLES . . . . . . . . . . . . . . . 18 3.1 Pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.1 Memory Organization for One Bit Pixel (Black-and-White 3.1.2 Memory Organization for Two Bit Pixels (4 Colors/Gray Shades 3.1.3 Memory Organization for Four Bit Pixels (16 Colors/Gray Shades ...
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... Page 4 5.6 Power Saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.6.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.6.2 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6 IDENTIFYING THE S1D13503 . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 7 PROGRAMMING THE S1D13503 . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7.1 Main Loop Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.2 Initialization Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.3 Advanced Functions 8 GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 S1D13503 X18A-G-002- Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/01/30 ...
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... Table 3-3: Look-Up Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 3-4: Look-Up Table Configurations .22 Table 3-5: S1D13503 Color Look-up Table For 256 Color Mode .23 Table 3-6: S1D13503 Black-To-White Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 3-7: S1D13503 Inverted Look-Up Table (White-To-Black .25 Table 3-8: S1D13503 Black-To-White Look-up Table For 4 Gray Shades . . . . . . . . . . . . . . . . . .26 Table 3-9: S1D13503 Low To High Intensity Color Look-Up Table For 4 Colors . . . . . . . . . . . . . .28 Table 3-10: Simulation Of First 16 Entries Of Standard VGA Palette ...
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... Page 6 S1D13503 X18A-G-002-06 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/01/30 ...
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... Figure 17: 320 x 240 Single Panel For Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 18: 640 x 480 Dual Panel For Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 19: Memory Map For A Dual Panel Showing A Single Image . . . . . . . . . . . . . . . . . . . . 51 Figure 20: Display For 13503DEMO.EXE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Programming Notes and Examples Issue Date: 01/01/30 LIST OF FIGURES Page 7 S1D13503 X18A-G-002-06 ...
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... Page 8 S1D13503 X18A-G-002-06 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/01/30 ...
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... Vancouver Design Center 1 INTRODUCTION The purpose of this guide is to demonstrate how to program the S1D13503 LCD controller, with reference made to the S5U13503B00C evaluation board. The first half of this guide presents the basic concepts of LCD controllers. The second half of this guide presents programming examples which are combined in a simple menu-driven program. Most of the program is written in the ‘ ...
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... Page 10 2 INITIALIZING THE S1D13503 This section presents two examples to show how to initialize the S1D13503 registers and write a pixel to the display. Code to initialize the S1D13503 is provided in Section 7.2, “Initialization Code” on page 60. The following examples describe values written to registers. • A “panel specific” value is one required for the given type of panel. Such a value must never change after initializa- tion of all registers. • ...
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... Evaluation Board Display Memory” on page 36 and Section 4.1, “Registers” on page 34 see Section 4.2.1, “S5U13503B00C Evaluation Board Display Memory” on page 36 and Section 4.1, “Registers” on page 34 see Section 5.4, “Split Screen” on page 45 see Section 5.1, “Virtual Displays” on page 40 S1D13503 X18A-G-002-06 ...
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... AUX[0Fh] 0000 1011 write Green data AUX[0Fh] 0000 1001 write Blue data AUX[0Eh] 0000 1100 increment palette address AUX[0Fh] 0000 0110 write Red data AUX[0Fh] 0000 0110 write Green data S1D13503 X18A-G-002-06 Epson Research and Development Vancouver Design Center Notes ...
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... Total Display Line Count Programming Notes and Examples Issue Date: 01/01/30 Notes Bits Per Pixel = ----------------------------------------------------------- - Horizontal Resolution Memory Interface Width 8 = ----- - 320 – 159 = 9Fh 16 = Number Of Display Lines 1 – = 240 1 Number Of Display Lines = -------------------------------------------------------------- 1 2 Page 13 See Also – 1 – = 239 = 0EFh – S1D13503 X18A-G-002-06 ...
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... The S5U13503B00C evaluation board maps the 128K of display memory into two banks of 64K, start- ing at D000:0000. This permits a VGA card to work along with the S1D13503B00C card. Bank 0 repre- sents the first 64K of display memory, and is selected by reading from the base port address+2. Bank 1 represents the second 64K of display memory, and is selected by writing to the base port address+2. The values read from or written to the base port address+2 are not important ...
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... Evaluation Board Display Memory” on page 36 and Section 4.1, “Registers” on page 34 see Section 4.2.1, “S5U13503B00C Evaluation Board Display Memory” on page 36 and Section 4.1, “Registers” on page 34 see Section 5.4, “Split Screen” on page 45 see Section 5.1, “Virtual Displays” on page 40 S1D13503 X18A-G-002-06 ...
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... AUX[0Eh] 0000 1100 increment palette address AUX[0Fh] 0000 0110 write Red data AUX[0Fh] 0000 0110 write Green data AUX[0Fh] 0000 1101 write Blue data AUX[0Eh] 0000 1101 increment palette address S1D13503 X18A-G-002-06 Epson Research and Development Vancouver Design Center Notes ...
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... Total Display Line Count Programming Notes and Examples Issue Date: 01/01/30 Notes Bits Per Pixel ----------------------------------------------------------- - = Horizontal Resolution Memory Interface Width 2 = ----- - 640 – 4Fh 16 = Number Of Display Lines 1 Number Of Display Lines 480 = -------------------------------------------------------------- 1 – = -------- - 1 2 Page 17 See Also – 1 – – = 239 = 0EFh 2 S1D13503 X18A-G-002-06 ...
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... Page 18 3 GRAY SHADES / COLORS AND LOOK-UP TABLES This section discusses how the S1D13503 shows color and monochrome images on LCD panels. 3.1 Pixels A pixel is physically stored in display memory as a series of bits. The more bits, the more colors the pixel can show. Table 3-1: Number Of Bits As Related To Colors ...
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... LUT. Eight bit pixels are only available in color panels. Programming Notes and Examples Issue Date: 01/01/30 Bit 4 Bit 3 Bit 2 Pixel 0 Pixel 1 Pixel 1 Bit 0 Bit 3 Bit 2 Bit 4 Bit 3 Bit 2 Green Bit 2 Green Bit 1 Green Bit 0 Page 19 Bit 1 Bit 0 Pixel 1 Pixel 1 Bit 1 Bit 0 Bit 1 Bit 0 Blue Bit 1 Blue Bit 0 S1D13503 X18A-G-002-06 ...
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... Bit 1 Bit 0 Bit 1 The S1D13503 has three internal 16 position, 4-bit wide Look-Up Tables (also referred to as palettes). The 4-bit value programmed into each table position determines the output gray shade / color weighting of display data. These tables are bypassed in black-and-white (BW) display mode. ...
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... Programming Notes and Examples Issue Date: 01/01/30 Look-Up Table Access bit 4 0 Auto-increment (see Note 1) 1 Red palette R/W access 0 Green palette R/W access 1 Blue palette R/W access Blue Bank Palette Data Palette Data Bit 0 Bit 3 Bit 2 Page 21 Palette Data Palette Data Bit 1 Bit 0 S1D13503 X18A-G-002-06 ...
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... For example, a pixel value of 00h would be black, E0h would be bright red, 1Ch would be bright green, and 03h would be bright blue. Because there are 16 entries for each color LUT, the S1D13503 provides two red banks, two green banks, and four blue banks in 256 color mode (see Section 3.2.8, “256 Colors (Eight Bits/Pixel in Color Mode)” ...
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... Epson Research and Development Vancouver Design Center 3.2.2.2 Monochrome Mode In monochrome mode, the S1D13503 treats the green LUT position, 4 bit wide monochrome LUT. Depending on the selected pixel size, this LUT will provide from banks. • 1 bit-per-pixel (black-and-white) In this format no LUT is used. A pixel value black, and a pixel value white. ...
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... Write LUT index to Look-Up Table Address Register AUX[0Eh]. 2. Write LUT entry value to Look-Up Table Data Register AUX[0Fh]. 3. Repeat steps 1 and 2 until all 16 LUT entries have been written. S1D13503 X18A-G-002-06 Table 3-6: S1D13503 Black-To-White Look-Up Table Look-Up Index Index Table (hex) (hex) ...
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... This example shows how to invert an image by changing only the LUT. Inverting means that pixels formally shown as light gray shades are now shown as dark gray shades, and vise versa. It does not matter whether the S1D13503 gray shade or 16 gray shade mode. ...
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... When the S1D13503 is configured for two bit pixels in monochrome mode, each pixel can index one of four monochrome LUT entries. Note that in monochrome mode, the S1D13503 uses the green LUT as the monochrome LUT. The 16 LUT entries are divided into four separate Look-Up tables or banks, each having four entries (see Figure 5). The following examples show how to program and select these banks ...
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... Look-Up Tables is not affected by the various ‘banking’ configurations. Figure 5: 4-Level Gray-Shade Mode Look-Up Table Architecture Programming Notes and Examples Issue Date: 01/01/30 Green Look-Up Table Bank Bank Bank 2 4-bit display data output 3 Select Bank 2 Logic Bank Page 27 S1D13503 X18A-G-002-06 ...
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... Four Colors (Two Bits/Pixel in Color Mode) When the S1D13503 is configured for two bit pixels in color mode, each pixel can index one of four color LUT entries. The 16 LUT entries are divided into four separate Look-Up tables or banks, each having four entries (see Figure 6). The following examples show how to program and select these banks ...
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... Blue Look-Up Table Bank Bank Bank 2 3 Select Bank 2 Logic Bank Page 29 4-bit ‘RED’ display data output 4-bit ‘GREEN’ display data output 4-bit ‘BLUE’ display data output S1D13503 X18A-G-002-06 ...
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... Page 30 3.2.6 Sixteen Gray Shades (Four Bits/Pixel in Monochrome Mode) When the S1D13503 has 4-bit monochrome pixels, each pixel can index into one of 16 LUT entries. The LUT bank bits are ignored in this mode. 16-Level Gray Shade Mode 4-bit pixel data ( P3, P2, P1 ...
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... Epson Research and Development Vancouver Design Center 3.2.7 Sixteen Colors (Four Bits/Pixel in Color Mode) When the S1D13503 has 4-bit color pixels, each pixel can index into each of the three color LUTs. The LUT bank bits are ignored in this mode. 16-Level Color Mode ...
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... Colors (Eight Bits/Pixel in Color Mode) When the S1D13503 has 8-bit color pixels, bits 7-5 represent the red LUT index, bits 4-2 represent the green LUT index, and bits 1-0 represent the blue LUT index (see Figure 9, “256-Level Color Mode Look-Up Table Architecture,” on page 33 recommended that the three LUTs are programmed according to Table 3-5, “ ...
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... Bank 7 display data output Select Bank 1 Logic Blue Look-Up Table Bank Bank 1 0 4-bit ‘BLUE’ 1 Bank 2 display data output 3 Select Bank 2 Logic Bank Page 33 S1D13503 X18A-G-002-06 ...
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... In a dual panel configuration, screen 1 refers to the upper half of the display. While in a single panel configuration, screen 1 refers to the first screen of the Split Screen Display feature where two differ- ent images (screen 1 and screen 2) can be displayed at the same time on one display. S1D13503 X18A-G-002-06 Gray Shade / ...
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... Display Display Display Start Addr Start Addr Start Addr Bit 12 Bit 11 Bit 10 ImageVerticalResolution MemoryInterfaceWidth ---------------------------------------------------------------- 2 8 Page 35 Screen 2 Screen 2 Display Display Start Addr Start Addr Bit 1 Bit 0 Screen 2 Screen 2 Display Display Start Addr Start Addr Bit 9 Bit 8 BytesPerPixel + Screen1DisplayStartAddress S1D13503 X18A-G-002-06 ...
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... Page 36 4.2 Description When displaying an image, the S1D13503 must read pixel data from display memory. This memory is organized to match the display resolution of the given LCD panel. To organize display memory, the following registers must be programmed: 1. Screen 1 Display Start Address Registers 2. Screen 2 Display Start Address Registers 3 ...
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... Compare the required number of bytes with the amount of memory available to the S1D13503. • The S1D13503 has 128k available, so there is 131,072 bytes available. Since this number is greater than the 76,800 bytes required for 640 x 480 with 4 colors, the S1D13503 implementation can support a 640 x 480 LCD with 4 colors. Note The memory required for 4 colors at 640 x 480 is the same as the memory required for 4 gray shades at 640 x 480 ...
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... Common Display Memory Requirements for LCD Panel Sizes: The following is a list of memory requirements and memory maps for common LCD resolutions. Note that the memory required for 640 x 480 with bits/pixel exceeds 128k and is therefore not supported on the S1D13503. Display ...
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... Scan Line 238 0001 2ABF 0001 2AC0 Scan Line 239 0001 2BFF Offset Offset (hex) (hex) 0000 Scan Line 0 013F 0140 Scan Line 1 027F F780 Scan Line 198 F8BF F8C0 Scan Line 199 F9FF Page 39 S1D13503 X18A-G-002-06 ...
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... Page 40 5 ADVANCED TECHNIQUES This section presents information on the following: • virtual displays • bitmaps and text displays • reading and writing to the S1D13503 registers • split screen displays • panning and scrolling • power saving 5.1 Virtual Displays This section presents a detailed description of the Address Pitch Adjustment Register, followed by a description of a virtual display ...
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... Epson Research and Development Vancouver Design Center 5.1.2 Description The S1D13503 can be programmed to wrap memory offsets in such a way that the physical display behaves as a viewport into a much larger “virtual” memory space. This viewport can be panned and/or scrolled to display this larger memory space. ...
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... When the program has completed writing the pix- els for the word “TEXT”, the display memory will have the data shown in Figure 15. In this figure the bytes are grouped within vertical lines. S1D13503 X18A-G-002-06 Figure 14: Font For The Message “TEXT” ...
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... Figure 15: Display Memory Contents For Message “Text” In 256 Color Mode 5.3 Mapping of Registers The S1D13503 has an internal set of 16-/8-bit read/write registers which configure it for various modes of operation. The registers can be accessed in two ways; Indexed Addressing and Direct Addressing. Note Refer to the S1D13503 Hardware Functional Specification (Document number X18A-A-001-xx) for more information on the S1D13503 registers ...
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... SRAM data lines VD[7 through 12]. See “Summary of Configuration Options” in the S1D13503 Hardware Functional Specification, Drawing Office No. X18A-A-001-xx. To access the internal 16 registers of the S1D13503, simply perform I/O read/write functions to the absolute address as defined in the previous paragraph. There is no memory banking available in direct addressing mode. ...
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... Issue Date: 01/01/30 Screen 1 Screen 1 Screen 1 Display Display Display Line Count Line Count Line Count Bit 4 Bit 3 Bit 2 n/a n/a n/a Page 45 Screen 1 Screen 1 Display Display Line Count Line Count Bit 1 Bit 0 Screen 1 Screen 1 Display Display Line Count Line Count Bit 9 Bit 8 S1D13503 X18A-G-002-06 ...
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... Program the Screen 1 Display Start Address Register to point to the beginning of image 1. Since image the beginning of display memory, program the Screen 1 Display Start Address Register to 0000h. AUX[06h] = 00h AUX[07h] = 00h 5. Calculate the total number of bytes required for image 1. bytes per scan line S1D13503 X18A-G-002-06 pixels per scan line 320 = --------------------------------------------- - = ...
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... Programming Notes and Examples Issue Date: 01/01/30 = base display memory address = D000:0000h, bank 0 + 0000:9600h = D000:9600h, bank 0 = Screen 1 Display Start Address 9600h = 0000h + -------------- - = 4B00h 2 visible scan lines 1 – = 240 1 – = 239 = + size of image 1 size of image 1 in bytes + -------------------------------------------------------- 2 bytes per word 00EFh X18A-G-002-06 Page 47 S1D13503 ...
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... Since image the beginning of display memory, program the Screen 1 Display Start Address Register to 0000h. AUX[06h] = 00h AUX[07h] = 00h 5. Calculate the total number of bytes required for image 1. bytes per scan line S1D13503 X18A-G-002-06 Scan Line 0 ... Image 1 Scan Line 99 Scan Line 100 ...
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... Write both image 1 and image 2 to their respective locations in display memory. Notes When using a dual panel, the Screen 1 Display Line Count Register is ignored by the S1D13503. Once the two Display Start Address Registers are programmed, the top panel will show the beginning of image 1, and the bottom panel will show the beginning of image 2 (see Figure 18) ...
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... Calculate the number of bytes per scan line. 4 gray shades => 2 bits per pixel 2 bits per pixel => 4 pixels per byte number of bytes per scan line S1D13503 X18A-G-002-06 = Screen 1 Display Start Address = Screen 2 Display Start Address ...
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... D000:0000h, bank 0 + 0000:9600h = D000:9600h, bank 0 480 = -------- - = 240 scan lines 2 2 640 = -------- - 240 = 38400 bytes = 9600h bytes 4 + size of first half of image X18A-G-002-06 Page 51 S1D13503 ...
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... To pan to the right, increase the value in the Screen 1 Display Start Address Register. To pan to the left, decrease the value in the Screen 1 Display Start Address Register. Note that the S1D13503 can pan right or left by either pixels. This is because the Screen 1 Display Start Address Register refers to either bytes or words (see Section 4.2.1, “S5U13503B00C Evaluation Board Display Memory” ...
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... Screen 1 Display Start Address + ---------------------------------------------------------------------------------------- - 320 = 0000h + -------- - 2 = 00A0h number of bytes in a virtual scan line = Screen 2 Display Start Address + ---------------------------------------------------------------------------------------- - Page 53 = 320 bytes per scan line 2 bytes per word 2 bytes per word S1D13503 X18A-G-002-06 ...
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... Page 54 5.6 Power Saving The following section introduces the power saving capabilities of the S1D13503. A detailed description of the Power Save Register is provided, followed by a description of the power save modes. 5.6.1 Registers Register bits discussed in this section are highlighted. AUX[03] Mode Register 1 I/O address = 0011b, Read/Write ...
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... Write ‘1’ to bit 7 of AUX[01h] to turn on the display. Programming Notes and Examples Issue Date: 01/01/30 Power Save Mode (PSM) PSM1 Normal (Active) State 1 State 2 Yes No No Yes Yes Yes Yes Yes No Yes Page 55 PSM2 No Yes No No Yes S1D13503 X18A-G-002-06 ...
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... Page 56 6 IDENTIFYING THE S1D13503 To identify the LCD controller upon power up / reset, perform the following steps: 1. Power up LCD controller. 2. Read AUX[0Eh], bits 5-4. Refer to Table 6-1 below to decode chip ID. Power On or RESET Note If the registers have already been initialized after power up, the ID bits in AUX[0Eh] cannot be used since these bits are also used for the RGB index ...
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... Vancouver Design Center 7 PROGRAMMING THE S1D13503 The purpose of this section is to show how to program the S1D13503 exercising the specific capabilities of this chip. A series of functions written in ‘C’ will be presented, each illustrating a basic feature of the S1D13503. These functions are written for the S5U13503B00C evaluation board, and are combined under a menu-driven program called 13503DEMO ...
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... ID_13502: printf("Detected S1D13502.\n\n"); Quit(); break; case ID_13502: printf("Detected S1D13502.\n\n"); Quit(); break; case ID_13503: printf("Detected S1D13503.\n"); break; default: printf("ERROR: Could not detect chip.\n\n"); Quit(); break; } ShowMenu(); while ((ch = getch()) != ESC) { switch (ch) ...
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... Epson Research and Development Vancouver Design Center break; case '2': GrayShadeBars(); break; case '3': SplitScreen(); break; case '4': PanScroll(); break; case '5': PowerSaving(); break; case ESC: exit(0 Programming Notes and Examples Issue Date: 01/01/30 Page 59 S1D13503 X18A-G-002-06 ...
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... Page 60 7.2 Initialization Code //------------------------------------------------------------------------- // // FUNCTION: Initialize DESCRIPTION: Intialize S1D13503 registers INPUTS: This function looks at the followingl global variables to // determine the appropriate register settings: // PanelX, PanelY, PanelType // // OUTPUTS: The following global variables are changed: // PanelGrayLevel, BytesPerScanLine // //------------------------------------------------------------------------- void Initialize(void) { static unsigned int val, val2; ...
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... WriteRegister(3, val2 BytesPerScanLine is a global variable // switch (PanelGrayLevel) { Programming Notes and Examples Issue Date: 01/01/30 x Horizontal Resolution // For black and white mode // For 4 gray shades/colors // For 16 gray shades/colors // For 256 colors // Line Byte/Word Count Register // Mode Register 1 Page S1D13503 X18A-G-002-06 ...
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... A dual panel LCD will, of course, have two panels. // show either the top or bottom half of the image, which is half of the // vertical resolution (PanelType == TYPE_DUAL) val /= 2; S1D13503 X18A-G-002-06 // Write to Mode Register; LCD Data Width = 4 bits Epson Research and Development Vancouver Design Center Each panel will ...
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... For convenience, set the screen 2 address WriteRegister(8, 0); WriteRegister(9, 0); } //-------------------------------------- // // Set Horizontal Non-Display Period use fixed default non-display period // WriteRegister(0x0c, 0); //-------------------------------------- Programming Notes and Examples Issue Date: 01/01/30 // Write to Total Display Line Count Reg // Scrn 1 Disp Line Count Reg (MSB) Page 63 S1D13503 X18A-G-002-06 ...
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... GetID This function returns the Chip ID. // //------------------------------------------------------------------------- static unsigned char GetID(int PortAddr) { static unsigned char ChipID; S1D13503 X18A-G-002-06 // Write to Address Pitch Adjustment Register // Auto-increment mode selected Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/01/30 ...
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... ChipID = ID_13503; break; case 0x20: ChipID = ID_13502; break; case 0x30: ChipID = ID_13502; break; default: ChipID = ID_NOT_DETECTED; break; } return(ChipID); } Programming Notes and Examples Issue Date: 01/01/30 Page 65 S1D13503 X18A-G-002-06 ...
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... Page 66 7.3 Advanced Functions #define VIRTUAL_X (360L) #define VIRTUAL_Y (360L) //------------------------------------------------------------------------- // // FUNCTION: ShowRegisters DESCRIPTION: Shows the contents of the S1D13503 registers INPUTS: None. // RETURN VALUE: None. // //------------------------------------------------------------------------- void ShowRegisters(void) { static unsigned char x; static unsigned char red, green, blue; printf("S1D13503 Registers: "); for ( < 16; ++x) printf(" ...
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... WriteRegister(3, val Update Line Byte/Word Count register for black and white Since black and white has 8 pixels per byte, there Programming Notes and Examples Issue Date: 01/01/30 // Set AUX[03] bit 2 // Clear AUX[03] bit 1 Page 67 S1D13503 X18A-G-002-06 ...
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... WriteRegister(3, val Update Lookup Table for 4 gray shades // for ( < 16; ++x) { WriteRegister(0x0e, x); WriteRegister(0x0f, MonoLUT4[x]); } S1D13503 X18A-G-002-06 // Line Byte Count Register // Clear bit 0 // Mode Register 1 // Clear AUX[01] bit 3 // Clear AUX[03] bits 1 and 2 Epson Research and Development Vancouver Design Center This means that ...
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... WriteRegister(3, val2); PanelGrayLevel = 4; ShowVerticalBars(pVideo, 0); // Programming Notes and Examples Issue Date: 01/01/30 // Clear AUX[01] bit 3 // Clear AUX[03] bit 2 // Set AUX[03] bit 1 // Line Byte Count Register // Clear bit 0 // Mode Register 1 Page 69 This means that S1D13503 X18A-G-002-06 ...
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... ReadRegister(1); val |= 0x08; WriteRegister(1, val); val = ReadRegister(3); val &= 0xf9; WriteRegister(3, val Update Lookup Table for 16 gray shades // S1D13503 X18A-G-002-06 // Set AUX[01] bit 3 // Clear AUX[03] bits 1 and 2 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/01/30 ...
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... ReadRegister(3); val2 &= 0xfe; val2 |= (val >> 8) & 0x01; WriteRegister(3, val2); Programming Notes and Examples Issue Date: 01/01/30 // Set AUX[01] bit 3 // Clear AUX[03] bit 2 // Set AUX[03] bit 1 // Line Byte Count Register // Clear bit 0 // Mode Register 1 Page 71 This means that S1D13503 X18A-G-002-06 ...
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... Since the Memory Interface is set to 16 bits, the Line Byte/Word Count // refers to words. // val = (PanelX / BytesPerScanLine = PanelX; WriteRegister(2, val & 0xff); S1D13503 X18A-G-002-06 // Set AUX[03] bits 1 and 2 // Line Byte Count Register Epson Research and Development Vancouver Design Center This means that ...
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... Each letter in the font bits // #define MAX_FONT 97 static const unsigned char font[MAX_FONT][ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, Programming Notes and Examples Issue Date: 01/01/30 // Clear bit 0 // Mode Register 1 Text must only contain All other // (blank) Page 73 S1D13503 X18A-G-002-06 ...
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... S1D13503 X18A-G-002-06 Epson Research and Development Vancouver Design Center // ! // " ...
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... Select Memory Bank by reading or writing to port (bank == 1) outp(PanelPortAddr+2, 0); Programming Notes and Examples Issue Date: 01/01/30 Page (backslash ‘ 127 // block char S1D13503 X18A-G-002-06 ...
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... Video |= (color << 4); if (val & 0x08) Video |= (color << 3); if (val & 0x04) Video |= (color << 2); if (val & 0x02) Video |= (color << 1); if (val & 0x01) S1D13503 X18A-G-002-06 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/01/30 ...
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... Video |= (color << 6); if (val & 0x40) Video |= (color << 4); if (val & 0x20) Video |= (color << 2); if (val & 0x10) Video |= color; *pVideo++ = (unsigned char) Video; CheckBank(pVideo, &bank); Programming Notes and Examples Issue Date: 01/01/30 // Point to next character Page 77 S1D13503 X18A-G-002-06 ...
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... Since there are 16 colors/gray shades, each bit in the font will be // represented in video memory as a four bit pixel (val & 0x80) Video |= (color << 4); if (val & 0x40) Video |= color; S1D13503 X18A-G-002-06 // Point to next character Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/01/30 ...
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... Video |= color; *pVideo++ = (unsigned char) Video; CheckBank(pVideo, &bank); pVideoFirstColumn += BytesPerScanLine; } pVideoStart += 4; pVideoFirstColumn = pVideoStart; } break; case 256: while (*str != *str++; if ((ch < ( > MAX_FONT-1 '.'; pFont = &font[ '][0]; for ( < 8; ++y) Programming Notes and Examples Issue Date: 01/01/30 // Point to next character Page 79 S1D13503 X18A-G-002-06 ...
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... ImageSize; static unsigned int OriginalLineCount; static unsigned int val; static int MinLineCount; static unsigned int MaxVirtualScanLines; static unsigned char Image2Bank; S1D13503 X18A-G-002-06 // Point to next character Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/01/30 ...
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... Because the image size is limited to a maximum of 320 x 240, and there // is 128k of video memory, there is enough memory available. // FP_SEG(pVideoImage2) = 0xd000; FP_OFF(pVideoImage2) = (unsigned int) (ImageSize & 0xffff); if (ImageSize & 0xffff0000) Image2Bank = BANK1; Programming Notes and Examples Issue Date: 01/01/30 Page 81 S1D13503 X18A-G-002-06 ...
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... Only for 128k of memory MaxVirtualScanLines = (unsigned int) ((unsigned long) 0x20000 / BytesPerScanLine); MinLineCount = OriginalLineCount - (MaxVirtualScanLines - OriginalLineCount (MinLineCount < 0) MinLineCount = Scroll image 2 down // for (val = MinLineCount; val < OriginalLineCount; val += 1) S1D13503 X18A-G-002-06 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/01/30 ...
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... Programming Notes and Examples Issue Date: 01/01/30 // Total Display Line Count // Total Disp Line Cnt/WF Count // Total Display Line Count // Total Disp Line Cnt/WF Count // Total Display Line Count Reg // Total Disp Line Cnt/WF Count Page 83 S1D13503 X18A-G-002-06 ...
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... Seed the random number generator with current time srand((unsigned) time(NULL)); for ( < 300; ++ (((rand() * 2L) / RAND_MAX bank = BANK0; else bank = BANK1; S1D13503 X18A-G-002-06 Epson Research and Development To do so, a text character will be used. Programming Notes and Examples Vancouver Design Center Issue Date: 01/01/30 ...
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... MaxY = (unsigned int) (VIRTUAL_Y - PanelY); SetDisplay(ON); for ( <= MaxX; ++x) { SetStartAddress(x, 0); Delay(DELAY_SHORT); } for ( <= MaxY; ++y) { SetStartAddress(MaxX, y); Delay(DELAY_SHORT); } for (x = MaxX; x > 0; --x) { SetStartAddress(x, MaxY); Delay(DELAY_SHORT); } for (y = MaxY; y > 0; --y) { SetStartAddress(0, y); Delay(DELAY_SHORT); } SetStartAddress(0, 0); Programming Notes and Examples Issue Date: 01/01/30 Page 85 S1D13503 X18A-G-002-06 ...
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... For the S5U13503B00C, wait about a half second. // Delay(500 Step 3: Enter Power Save Mode // val = ReadRegister(3); val &= 0x3f; val |= 0x80; WriteRegister(3, val); // Set power saving mode 2 S1D13503 X18A-G-002-06 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/01/30 ...
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... Step 2: Enable LCDE (turn on LCD power supply). // For the S5U13503B00C, set LCDE bit val = ReadRegister(1); val |= 0x10; WriteRegister(1, val Step 3: Turn on display. // val = ReadRegister(1); val |= 0x80; WriteRegister(1, val); ShowMenu(); } Programming Notes and Examples Issue Date: 01/01/30 Page 87 S1D13503 X18A-G-002-06 ...
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... The up and down movement of the viewport in a virtual display. S1D13503 The 13503 chip. S5U13503B00C The evaluation board for the S1D13503. The S5U13503B00C is an ISA board for a PC- compatible computer. viewport The visible portion of a virtual display. virtual display An image, which is stored in display memory, that is larger than what the LCD display can show ...
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... Bit 8 1 n/a bits should be written 0. 2 These bits are used to identify the S1D13503 at power on / RESET. If these bits read 00b at Power On / Reset the device is an S1D13503F00A. If this bit reads 10b at Power On / Reset the device is an S1D13502F00B. If this bit reads 11b at Power On / Reset the device is an S1D13502F00A. ...
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... S1D13503F00A Register Summary Page 2 X18A-Q-002-05 01/03/02 ...
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... S1D13503 Dot Matrix Graphics LCD Controller 13503SHOW.EXE Display Utility Document Number: X18A-B-001-05 Copyright © 1997, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13503 X18A-B-001-05 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center 13503SHOW.EXE Display Utility Issue Date: 01/01/29 ...
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... Epson Research and Development Vancouver Design Center 13503SHOW.EXE DISPLAY UTILITY 13503SHOW is a utility used to load and display GIF images. It can also be used to demonstrate the split screen capabilities of the S1D13503 by loading two images and vertically scrolling one image. Program Requirements Video Controller Display Type ...
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... File is not GIF89a format. The GIF file contains an invalid format. 1350313503SHOW only supports GIF89a format. Insufficient video memory for second image. There is not enough video memory available to store both images. S1D13503 X18A-B-001-05 Epson Research and Development Vancouver Design Center with no arguments will run the program in split screen mode. ...
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... S1D13503 Dot Matrix Graphics LCD Controller 13503VIRT.EXE Display Utility Document Number: X18A-B-002-05 Copyright © 2001Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13503 X18A-B-002-05 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center 13503VIRT.EXE Display Utility Issue Date: 01/01/29 ...
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... Vancouver Design Center 13503VIRT.EXE DISPLAY UTILITY 13503VIRT.EXE demonstrates the virtual panning capabilities of the S1D13503. Two images larger than the display resolution are loaded in display memory. 13503VIRT.EXE will then display split screen, a portion of each complete image while providing panning capabilities using the arrow keys for navigation. ...
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... Program Messages ERROR: This program requires 13503BIOS to be loaded! The program 13503BIOS.COM must be run before 13503VIRT.EXE. Load 13503BIOS.COM and then re-run 13503VIRT.EXE. S1D13503 X18A-B-002-05 Epson Research and Development Vancouver Design Center 13503VIRT.EXE Display Utility ...
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... S1D13503 Dot Matrix Graphics LCD Controller 13503BIOS.COM Utility Document Number: X18A-B-003-05 Copyright © 1995, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13503 X18A-B-003-05 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center 13503BIOS.COM Utility Issue Date: 01/01/29 ...
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... INT 10h. This program provides text, scroll, and cursor functionality when no VGA BIOS is present. Although the S1D13503 is not a VGA or EGA compatible controller, this program is supplied to give the user a familiar prompt. Within limits 13503BIOS simulates a VGA BIOS and will allow standard output functions to work. DOS programs such as Edlin, Format, Debug, and internal commands such as Copy, Ren, Mkdir, etc ...
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... The panel specified is too large to run in 16 gray shades mode. Select 4 gray shades instead. ERROR: Video memory and VGA BIOS memory conflict. Both the S1D13503 video memory and the VGA BIOS are trying to use the memory at location C000h to CFFFh. ERROR: only 64k or 128k memory allowed. ...
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... S1D13503 Dot Matrix Graphics LCD Controller 13503MODE.EXE Display Utility Document Number: X18A-B-004-05 Copyright © 1997, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13503 X18A-B-004-05 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center 13503MODE.EXE Display Utility Issue Date: 01/01/29 ...