NCV8141 ON Semiconductor, NCV8141 Datasheet - Page 7

• Manufacturer Part Number: NCV8141
• Description: 5v, 500ma Linear Regulator With Enable, /reset, And Watchdog
• Manufacturer: ON Semiconductor

through the NPN pass transistor is monitored. Feedback
circuitry insures that the output current never exceeds a
preset limit.
exceed 180°C (typ), the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
unique combination of control features.
Watchdog and ENABLE Function
Watchdog (Table 1).
Watchdog signal is normal, V
ENABLE is low and the frequency of the Watchdog input
goes below the threshold frequency, the output transistor
turns off and the IC goes into SLEEP mode. Only the
ENABLE
V
Table 1. V
Using an emitter sense scheme, the amount of current
Should the junction temperature of the power device
The NCV8141 differs from all other linear regulators in its
V
As long as ENABLE is high or ENABLE is low and the
OUT
V
I
IN
OUT
Figure 8. Typical Circuit Waveforms for Output
H
O
L
is controlled by the logic functions ENABLE and
REGULATOR CONTROL FUNCTIONS
Dump
> 30 V
Load
OUT
Slow
as a Function of ENABLE and Watchdog
5
0
Stage Protection
Circuit
Short
Normal
V
OUT
5
5
OUT
(V)
WDI
will be at 5.0 V (typ). If
High
Shutdown
Thermal
5
0
Low
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5
0
NCV8141
7
ENABLE circuitry in the IC remains powered up, drawing
a quiescent current of less than 50 mA.
WDI signal. If the signal falls below the WDI limit, a
frequency programmable pulse train is generated at the
RESET lead (Figure 9) until the correct Watchdog input
signal reappears at the lead (ENABLE = HIGH).
value of C
following equation for the NCV8141:
the RESET signal and the POWER-ON-RESET (POR)
delay period.
RESET Function
frequency signal is below the watchdog threshold
(Figure 9), when the regulator is in its power up state
(Figure 10) or when V
more than 2.0 ms (Figure 11)
or
programmable pulse train is generated at the RESET lead
(Figure 9) until the correct Watchdog input signal reappears
at the lead. The duration of the RESET pulse is determined
by C
RESET lead goes low and the delay capacitor, C
discharged. RESET remains low until output is in
regulation, the voltage on C
threshold and the Watchdog input signal is valid (Figures 10
and 11). The delay after the output is in regulation is:
external cap C
RESET is operational down to V
and its delay are governed by comparators with hysteresis to
avoid undesirable oscillations.
The Watchdog monitors the frequency of an incoming
The threshold limit of the watchdog function is set by the
The capacitor C
The RESET function is activated when the Watchdog
If the Watchdog signal falls outside of the preset voltage
If an undervoltage condition exists, the voltage on the
The RESET delay circuit is also programmed with the
The output of the reset circuit is an open collector NPN.
below
DELAY
RESET CIRCUIT WAVEFORMS WITH DELAYS
t WDI(RESET) + (1.0
DELAY
t POR(typ) + (4.75
according to the following equation:
t WDI + (1.3
the
DELAY
. The limit is determined according to the
DELAY
frequency
.
OUT
INDICATED
also determines the frequency of
10 5) C DELAY or
drops below V
DELAY
threshold,
OUT
10 4) C DELAY
10 5) C DELAY
= 1.0 V. Both RESET
exceeds the upper
OUT
a
-4.5% for
frequency
DELAY
, is