HV623 Supertex, Inc., HV623 Datasheet

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HV623

Manufacturer Part Number
HV623
Description
32-channel 128-level Amplitude Gray-shade Display Column Driver
Manufacturer
Supertex, Inc.
Datasheet
Features
Ordering Information
Absolute Maximum Ratings
Supply voltage, V
Supply voltage, V
Logic input levels
Ground current
Continuous total power dissipation
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
Notes:
1. All voltages are referenced to GND.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25 C ambient derate linearly to 70 C at 22.2mW/ C.
5V CMOS inputs
Up to 80V modulation voltage
Capable of 128 levels of gray shading
20MHz data throughput rate
32 outputs per device (can be cascaded)
Pin-programmable shift direction (DIR)
D/A conversion cycle time is 32 s
Diodes in output structure allow usage
in energy recovery systems
Integrated HVCMOS
Available in 3-sided 64-lead gullwing package
Device
HV623
2
1
DD
PP
1
1
32-Channel 128-Level Amplitude Gray-Shade
®
technology
64-Lead 3-sided Plastic Gullwing
3
Package Option
HV623PG
Display Column Driver
-0.5 to V
-65 C to +150 C
-40 C to +70 C
-0.5V to +7.5V
-0.5V to +90V
DD
+ 0.5V
260 C
1.5A
1W
12-122
General Description
The HV623 is a 32-channel driver IC for gray shade display use.
It is designed to produce varying output voltages between 3 and
80 volts. This amplitude modulation at the output is facilitated by
an external ramp voltage V
explanation.
This device consists of a dual 16-bit shift registers, 32 data latches
and comparators, and control logic to preform 128 levels of gray
shading. There are 7 bits of data inputs. Data is shifted through the
shift registers at both edges of the clock, resulting a data transfer
rate of twice of the shift clock frequency. When the DIR pin is high,
CSI/CSO is the input/output for the chip select pulse. When DIR
is low, CSI/CSO is the output/input for the chip select pulse. The
DIR = HIGH also allows the HV623 to shift data in the counter-
clockwise direction when viewed from the top of the package.
When the DIR pin is low, data is shifted in the clockwise direction.
The output circuitry allows the energy which is stored in the output
capacitance to be returned to V
output transistor.
R
. See Theory of Operation for detailed
PP
through the body diode of the
HV623

Related parts for HV623

HV623 Summary of contents

Page 1

... CSI/CSO is the input/output for the chip select pulse. When DIR is low, CSI/CSO is the output/input for the chip select pulse. The DIR = HIGH also allows the HV623 to shift data in the counter- clockwise direction when viewed from the top of the package. When the DIR pin is low, data is shifted in the clockwise direction. ...

Page 2

... Table 1. Max Units Conditions 80V PP See test circuit 80V 0 all gray levels Min Typ Max 4.5 5.0 5.5 4.5 5 10.2 - HV623 = max = 4.5V Units MHz C ...

Page 3

... Units Conditions 10.2 MHz 20.4 MHz ramp from 0 to 3V, assuming the minimum value Typ Max Units Conditions will droop due to leakage. V CTL HV623 V CTL - + R CTL R CTL - + V BIAS HV623 , RR ...

Page 4

... 32. When connected to LVGND, input data is shifted OUT OUT OUT and R CTL CTL function above. CTL V DD GND (Logic) 12-125 ). H 1. OUT CTL will reduce the output voltage variation to less than Data Out Logic Data Output HV623 = 2V for a ...

Page 5

... RS Output F/F Stage 7 Output RS F/F Stage 7 RS Output F/F Stage 7 RS Output F/F Stage Clear 7 Counter Count Reset Counter Load Clear Load Count Pulse Count Clock Generator Buffer Buffer LC CC HV623 ) HV OUT + 1K V tst - 10K OUT HV 2 OUT HV 31 OUT HV 32 OUT CC ...

Page 6

... Clock Cycle HV623 OUT HV OUT HV OUT HV OUT HV OUT ...

Page 7

... Device Data from Data Bus (See Detailed Timing) t DLCR 128 12-128 Shift Load Count V R Clock Count Clock Initiates V RAMP Load Last Device HV623 HV OUT 128 ...

Page 8

... 12-129 NEXT LOADING CYCLE SC 1 DATA SET 1 t DSL t WLC Count Clock 1 t DRCC t DLCR 3V 0V Sink Output Characteristics Volts GS HV623 SC 16 DATA SET 31 t WCC t CCC Count Clock 128 80V 7 8 ...

Page 9

... Since the device was developed initially for flat panel displays, the operation will be described in terms that pertain to that technol- ogy. As shown by the Typical Drive Scheme, several HV623 packages are mounted at the top and bottom of a display panel. Data exists on a 7-bit bus (adjacent PC board traces) at top and bottom ...

Page 10

... R will be at the final value. (See Output Gray Scale Voltage.) Output Voltage Variation The output voltage of the HV623 is determined by the logic and the ramp voltage V coupled to an unacceptable level due to its adjacent outputs through the panel. In order to solve this problem, internal logic (refer to Output Stage Detail) is integrated in the IC to minimize the effect ...

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