LMX2364 National Semiconductor Corporation, LMX2364 Datasheet

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LMX2364

Manufacturer Part Number
LMX2364
Description
2.6 Ghz Pllatinum Fractional Rf Frequency Synthesizer With 850 Mhz Integer If Frequency Synthesizer
Manufacturer
National Semiconductor Corporation
Datasheet

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© 2003 National Semiconductor Corporation
LMX2364
2.6 GHz PLLatinum Fractional RF Frequency Synthesizer
with 850 MHz Integer IF Frequency Synthesizer
General Description
The LMX2364 integrates a high performance 2.6 GHz frac-
tional frequency synthesizer with a 850 MHz low power
Integer-N frequency synthesizer. Designed for use in a local
oscillator subsystem of a radio transceiver, the LMX2364
generates very stable, low noise control signals for UHF and
VHF voltage controlled oscillators. It is fabricated using Na-
tional’s high performance BiCMOS process.
The RF Synthesizer supports both fractional and integer
modes. The N counter contains a selectable, quadruple
modulus prescaler and can support fractional denominators
from 1 to 128. A flexible, 4 level programmable charge pump
supplies output current magnitudes ranging from 1 mA to 16
mA. Only a single word write is required to power up and
tune the synthesizer to a new frequency.
High performance FastLock
LMX2364 an excellent choice for applications requiring ag-
gressive lock time while maintaining excellent phase noise
and spurious performance. The combination of the improved
FastLock circuitry, the enhanced fractional compensation
engine, and the programmable charge pump architecture
gives the designer maximum freedom to optimize the perfor-
mance of the synthesizer for the target application. Inte-
grated timeout counters greatly simplify the programming
aspects of FastLock. These timeout counters reduce the
demands on the microcontroller by automatically disengag-
ing FastLock after a perscribed number of reference cycles
of the phase detector.
The IF synthesizer includes a fixed 8/9 dual modulus pres-
caler, a two level programmable charge pump, and dedi-
cated FastLock circuitry with an integrated timeout counter.
The LMX2364 offers many performance enhancements over
the LMX2354. Improvements in the fractional compensation
make the spurs on the LMX2364 approximately 6 dB better
in a typical application. The higher and more flexible frac-
tional modulus combined with the higher charge pump cur-
rents result in phase noise improvements on the order of 10
dB. The cycle slip reduction circuitry of the LMX2364 is both
easy to use and effective in reducing cycle slipping and
allows one to use very high phase detector frequencies
without degrading lock times.
Serial data is transferred to the device via a three-wire
interface (DATA, LE, CLK). The low voltage logic interface
FastLock
TRI-STATE
®
is a trademark of National Semiconductor Corporation.
is a registered trademark of National Semiconductor Corporation.
technology makes the
DS200506
allows direct connection to 1.8 Volt and 3.0 Volt devices.
Supply voltages from 2.7V to 5.5V are supported. Indepen-
dent charge pump supplies for each synthesizer allows the
designer to optimize the bias level for the selected VCO. The
LMX2364 consumes 5.0 mA (typical) of current in integer
mode and 7.2 mA (typical) in fractional mode. The LMX2364
is available in a 24 Pin Ultra Thin CSP package and 24 Pin
TSSOP Package.
Features
n RF Synthesizer supports both Fractional and Integer
n Pin Compatible upgrade for LMX2354
n 2.7V to 5.5V operation
n Pin and programmable power down
n Fractional N divider supports fractional denominators
n Supports Integer Mode Operation
n Programmable charge pump current levels
n FastLock Technology with integrated timeout counters
n Digital filtered & analog lock detect output
n FastLock Glitch Reduction Technology
n Enhanced Low Noise Fractional Compensation Engine
n Low voltage programming interface allows direct
Applications
n Digital Cellular
n GPRS
n IS-136
n GAIT
n PDC
n EDGE
n CDMA
n Zero blind slot TDMA systems
n Cable TV Tuners (CATV)
Operating Modes
ranging from 1 through 128
connection to 1.8V logic
RF: 4 level, 1 – 16 mA
IF: 2 level, 100/800 uA
www.national.com
July 2003

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LMX2364 Summary of contents

Page 1

... The cycle slip reduction circuitry of the LMX2364 is both easy to use and effective in reducing cycle slipping and allows one to use very high phase detector frequencies without degrading lock times ...

Page 2

Functional Block Diagram Connection Diagrams 24-Pin TSSOP (TM) Package www.national.com Ultra Thin 24-Pin CSP (SLE) Package 20050602 2 20050601 20050622 ...

Page 3

Pin Descriptions Pin Number Pin TSSOP SLE 2 1 VccRF 3 2 VcpRF 4 3 CPoutRF 5 4 GND 6 5 FinRF 7 6 FinRF GND 9 8 OSCinRF 10 9 OSCinIF 11 10 Ftest/ ENRF ...

Page 4

Absolute Maximum Ratings Parameter Power Supply Voltage Voltage on any pin with GND = 0V Storage Temperature Range Lead Temperature (Solder 4 sec.) Recommended Operating Conditions Parameter Power Supply Voltage Operating Temperature Note 1: “Absolute Maximum Ratings” indicate limits beyond ...

Page 5

Electrical Characteristics Symbol Parameter RF SYNTHESIZER PARAMETERS I SRCE RF Charge Pump Source CPoutRF Current I SINK RF Charge Pump Sink CPoutRF Current I TRI RF Charge Pump CPoutRF TRI-STATE Current I %MIS RF CP Sink vs. CP Source CPoutRF ...

Page 6

Electrical Characteristics Symbol Parameter OSCILLATOR PARAMETERS f Oscillator Operating OSC Frequency v Oscillator Sensitivity OSC I Oscillator Input Current OSC DIGITAL INTERFACE (DATA, CLK, LE, ENIF, ENRF, Ftest/LD, FLoutRF, FLoutIF) V High-Level Input Voltage IH V Low-Level Input Voltage IL ...

Page 7

Serial Data Input Timing Note: Data is shifted MSB first into the MICROWIRE shift register on the rising edge of the Clock signal. When a rising edge is seen on the LE pulse, these values are actually loaded into the ...

Page 8

Typical Performance Characteristics RF PLL 1 Hz Normalized Phase Noise (Fractional Mode) www.national.com IF PLL 1 Hz Normalized Phase Noise 8 20050672 20050673 ...

Page 9

Typical Performance Characteristics (Continued Counter Sensitivity T = 25˚ Counter Sensitivity Vcc = 3.0V 9 20050645 20050646 www.national.com ...

Page 10

Typical Performance Characteristics www.national.com (Continued Counter Sensitivity T = 25˚ Counter Sensitivity Vcc = 3.0V 10 20050647 20050648 ...

Page 11

Typical Performance Characteristics (Continued) OSCinRF Counter Sensitivity T = 25˚C A OSCinRF Counter Sensitivity Vcc = 3.0V 11 20050649 20050650 www.national.com ...

Page 12

Typical Performance Characteristics www.national.com (Continued) OSCinIF Counter Sensitivity T = 25˚C A OSCinIF Counter Sensitivity Vcc = 3.0V 12 20050651 20050652 ...

Page 13

Input Impedance: FinRF Pin CSP Package Frequency (MHz) 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 20050653 FinRF Input Impedance (Ohms) CSP Package Real Imaginary 195 -234 128 -183 98 -152 77 -125 67 -106 59 -92 ...

Page 14

Input Impedance: FinIF Pin CSP Package Frequency (MHz) 100 200 300 400 500 600 700 800 900 1000 1100 1200 www.national.com 20050657 FinIF Input Impedance (ohms) CSP Package Real Imaginary 504 -279 374 -280 283 -270 222 -250 179 -230 ...

Page 15

Input Impedance: OSCinIF Pin CSP Package Frequency CSP Package (MHz) Powered Up Real Imaginary 10 338 -2741 25 130 -1098 50 97 -552 75 89 -366 100 84 -276 110 83 -251 20050655 OSCinIF Input Impedance (ohms) Powered Down Powered ...

Page 16

Typical Performance Characteristics www.national.com Total Current Consumption RF_OM=1 Powerdown Current ENRF ENIF 16 20050660 20050661 ...

Page 17

Typical Performance Characteristics (Continued) RF Charge Pump Current V = 3.0V VcpRF RF Charge Pump Current V = 5.0V VcpRF 17 20050667 20050668 www.national.com ...

Page 18

Typical Performance Characteristics www.national.com (Continued) IF Charge Pump Current V = 3.0V VcpIF IF Charge Pump Current V = 5.0V VcpIF 18 20050665 20050666 ...

Page 19

Typical Performance Characteristics (Continued) Charge Pump Leakage RF PLL Charge Pump Leakage IF PLL 19 20050664 20050663 www.national.com ...

Page 20

... The factor of two comes in because the LMX2364 has a flip-flop which divides this frequency by two to make the duty cycle 50% in order to make it easier to read with the frequency counter. The frequency counter input impedance should be set to high impedance ...

Page 21

Charge Pump Currents The above block diagram shows the test procedure for test- ing the RF and IF charge pumps. These tests include abso- lute current level, mismatch, and leakage. In order to mea- sure the charge pump currents, a ...

Page 22

... Input Impedance The above block diagram shows the test procedure measur- ing the input impedance for the LMX2364. This applies to the FinRF, FinIF, OSCinRF, and OSCinIF pins. The input imped- ance of the CSP and the TSSOP package should always be assumed to be different, until proven otherwise. The basic ...

Page 23

... OPERATING MODES The LMX2364 RF PLL is a capable of operating as both a Fractional N synthesizer and an Integer N synthesizer. Op- erating in Fractional mode is likely to yield the best phase noise, but Integer mode often yields the lowest spur levels. ...

Page 24

Programming Description 2.0 INPUT DATA REGISTER The 24-bit input data register is loaded through the MICROWIRE Interface. The input data register is used to program the control registers. The data format of the 24-bit data register is shown below. The ...

Page 25

Programming Description 2.3 R0 REGISTER Reg IF_ IF_ IF_ RST CP CPP 2.3.1 IF_R[14:0] — R Divider Ratio, IF Synthesizer The R0 control word is used to configure the ...

Page 26

Programming Description 2.4 R1 REGISTER This register is used to configure the N divider for the IF synthesizer. A single word write to this register is all that is required to power up and tune the synthesizer to the desired ...

Page 27

Programming Description 2.5 R2 REGISTER The R2 Register is used to setup the FastLock circuitry for the IF synthesizer. Reg 2.5.1 IF_TOC[13:0] — FastLock Timeout ...

Page 28

Programming Description 2.6 R3 REGISTER The R3 register is used to setup the RF R Divider ratio as well as several other control functions related to the RF synthesizer. Reg RF_ RF_ RF_ RF_ ...

Page 29

Programming Description 2.6.3 RF_CP[1:0] — Charge Pump Gain, RF Synthesizer The RF_CP word is used to control the charge pump gain for the RF synthesizer. Four different CP gains are supported ranging from mA. Note that when ...

Page 30

Programming Description 2.7 R4 REGISTER This register is used to setup the N divider for the RF Synthesizer. A single word write to this register is all that is required to power up and tune the RF synthesizer to the ...

Page 31

... Both synchronous and asynchronous power down modes are available with the LMX2364 in order to adapt to different types of applications. The power down mode bit R6[8] is used to select between synchronous and asynchronous power down. The MICROWIRE control register remains active and capable of loading and latching in data in either power down mode ...

Page 32

Programming Description 2.8 R5 REGISTER The R5 Register is used to setup and control the FastLock circuitry for the RF synthesizer. Reg RF_ RF_ RF_ R5 0 CSR[1:0] OM[1:0] CPF[1:0] 2.8.1 RF_TOC[13:0] — FastLock ...

Page 33

Programming Description 2.9 R6 REGISTER Reg 2.9.1 MUX[3:0] — Coltrol Word for the Ftest/LD Pin The MUX[3:0] control word is used to determine the function ...

Page 34

Supplemental Information 3.0 USE OF THE DIGITAL LOCK DETECT FUNCTION The Lock Detect Digital Filter compares the difference be- tween the phase of the inputs of the phase detector generated delay of approximately 15nS. To enter the ...

Page 35

... PLL. 100 typical value. 3.2 FASTLOCK AND CYCLE SLIP REDUCTION CIRCUITRY OPERATION The LMX2364 has enhanced features for FastLock opera- tion. When the PLL is switching frequencies, the charge pump current and comparison frequencies may be adjusted. The purpose of increasing the charge pump current is to increase the loop bandwidth ...

Page 36

... If increasing the loop bandwidth during frequency acquisition is not sufficient to reduce cycle slip- ping, the LMX2364 also has a routine to decrease the com- parison frequency. 36 Theoretical Lock Time Multiplier x 2 ...

Page 37

... FastLock. 3.6 CAPACITOR DIELECTRIC CONSIDERATIONS The LMX2364 has a high fractional modulus and high charge pump gain for the lowest possible phase noise. One consideration is that the reduced N value and higher charge pump may cause the capacitors in the loop filter to become larger in value ...

Page 38

... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted Thin Shrink Small Outline (TSSOP) Package Order Number LMX2364TM (Rail) Order Number LMX2364TMX (Tape and Reel) NS Package Number MTC24 38 ...

Page 39

... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted (Continued) Ultra Thin Chip Scale Package (SLE) For Tape and Reel (2500 Units per Reel) Order Number LMX2364SLEX NS Package Number SLE24A 2. A critical component is any component of a life support device or system whose failure to perform ...

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