LMX2470 National Semiconductor Corporation, LMX2470 Datasheet

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LMX2470

Manufacturer Part Number
LMX2470
Description
2.6 Ghz Delta-sigma Fractional-n Pll With 800 Mhz Integer-n Pll
Manufacturer
National Semiconductor Corporation
Datasheet

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© 2003 National Semiconductor Corporation
LMX2470
2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz
Integer-N PLL
General Description
The LMX2470 is a low power, high performance delta-sigma
fractional-N PLL with an auxiliary integer-N PLL. The device
is fabricated using National Semiconductor’s advanced BiC-
MOS process.
With delta-sigma architecture, fractional spur compensation
is achieved with noise shaping capability of the delta-sigma
modulator and the inherent low pass filtering of the PLL loop
filter. Fractional spurs at lower frequencies are pushed to
higher frequencies outside the loop bandwidth. Unlike ana-
log compensation, the digital feedback techniques used in
the LMX2470 are highly resistant to changes in temperature
and variations in wafer processing. With delta-sigma archi-
tecture, the ability to push close in spur and phase noise
energy to higher frequencies is a direct function of the modu-
lator order. The higher the order, the more this energy can be
spread to higher frequencies. The LMX2470 has a program-
mable modulator up to order four, which allows the designer
to select the optimum modulator order to fit the phase noise,
spur, and lock time requirements of the system.
Programming is fast and simple. Serial data is transferred
into the LMX2470 via a three line MICROWIRE interface
(Data, Clock, Load Enable). Nominal supply voltage is 2.5 V.
The LMX2470 features a typical current consumption of 4.1
mA at 2.5 V. The LMX2470 is available in a 24 lead 3.5 X 4.5
X 0.6 mm package.
Functional Block Diagram
DS200593
Features
n Low in-band phase noise and low fractional spurs
n 12 bit or 22 bit selectable fractional modulus
n Up to 4th order programmable delta-sigma modulator
n Enhanced Anti-Cycle Slip Fastlock Circuitry
n Digital lock detect output
n Prescalers allow wide range of N values
n Crystal Reference Frequency up to 110 MHz
n On-chip crystal reference frequency doubler.
n Phase Comparison Frequency up to 30 MHz
n Hardware and software power-down control
n Ultra low consumption: I
Applications
n Cellular Phones and Base Stations
n Applications requiring fine frequency resolution
n Satellite and Cable TV Tuners
n WLAN Standards
Fastlock
Cycle slip reduction
Integrated timeout counters
RF PLL: 16/17/20/21
IF PLL: 8/9 or 16/17
CDMA, WCDMA, GSM/GPRS, TDMA, EDGE, PDC
CC
= 4.1 mA (typical)
20059301
www.national.com
April 2003

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LMX2470 Summary of contents

Page 1

... Programming is fast and simple. Serial data is transferred into the LMX2470 via a three line MICROWIRE interface (Data, Clock, Load Enable). Nominal supply voltage is 2.5 V. The LMX2470 features a typical current consumption of 4 2.5 V. The LMX2470 is available lead 3.5 X 4.5 X 0.6 mm package. Functional Block Diagram © 2003 National Semiconductor Corporation ...

Page 2

Connection Diagram Pin Descriptions Pin # Pin I/O Name 1 CPoutRF O RF charge pump output. 2 GND - Ground 3 GND - RF Ground 4 GND - Ground for RF PLL digital circuitry. 5 FinRF I RF prescaler input. ...

Page 3

Absolute Maximum Ratings Parameter Power Supply Voltage Voltage on any pin with GND = Storage Temperature Range Lead Temperature (Solder 4 sec.) Recommended Operating Conditions Parameter Power Supply Voltage (Note 1) Operating Temperature Note 1: “Absolute Maximum ...

Page 4

Electrical Characteristics Symbol Parameter RF SYNTHESIZER PARAMETERS I SINK RF Charge Pump Sink CPoutRF Current I TRI RF Charge Pump CPoutRF TRI-STATE Current Magnitude I %MIS RF CP Sink vs. CP Source CPoutRF Mismatch Current vs. ...

Page 5

Electrical Characteristics Symbol Parameter DIGITAL INTERFACE (DATA, CLK, LE, EN, ENRF, Ftest/LD, FLoutRF, FLoutIF) V Low-Level Output Voltage OL MICROWIRE INTERFACE TIMING T Data to Clock Set Up Time CS T Data to Clock Hold Time CH T Clock Pulse ...

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Typical Performance Characteristics : Sensitivity www.national.com (Note Counter Sensitivity T = 25˚ Counter Sensitivity 20059345 20059346 ...

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Typical Performance Characteristics : Sensitivity (Note Counter Sensitivity T = 25˚ Counter Sensitivity (Continued) 20059347 20059348 www.national.com ...

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Typical Performance Characteristics : Sensitivity www.national.com (Note 4) OSCin Counter Sensitivity OSC 25˚C A OSCin Counter Sensitivity OSC 2 (Continued) 20059349 20059350 ...

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Typical Performance Characteristic : FinRF Input Impedance Frequency (MHz) 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 FinRF Input Impedance Real (Ohms) ...

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Typical Performance Characteristic : FinIF Input Impedance Freqeuncy (MHz) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 900 1000 www.national.com FinIF Input Impedance Real (Ohms) 580 500 445 410 378 349 322 ...

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Typical Performance Characteristic : OSCin Input Impedance Frequency (MHz 100 110 OSCin Input Impedance Real (Ohms) Imaginary (Ohms) 2200 -4700 710 -2700 229 -1500 133 -988 93 -752 74 -606 ...

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Typical Performance Characteristics : Currents www.national.com (Note 4) Total Current Consumption OSC=0 Powerdown Current EN = LOW 12 20059359 20059361 ...

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Typical Performance Characteristics : Currents (Note 4) RF Charge Pump Current V = 2.5 Volts CC IF Charge Pump Current V = 2.5 Volts CC 13 (Continued) 20059367 20059365 www.national.com ...

Page 14

Typical Performance Characteristics : Currents Note 4: Typical performance characteristics do not imply any sort of guarantee. Guaranteed specifications are in the electrical characteristics section. www.national.com (Note 4) Charge Pump Leakage RF PLL Charge Pump Leakage IF PLL 14 (Continued) ...

Page 15

Bench Test Setups Charge Pump Current Measurement Procedure The above block diagram shows the test procedure for test- ing the RF and IF charge pumps. These tests include abso- lute current level, mismatch, and leakage. In order to mea- sure ...

Page 16

... The factor of two comes in because the LMX2470 has a flip-flop which divides this frequency by two to make the duty cycle 50% in order to make it easier to read with the frequency counter. The frequency counter input impedance should be set to high impedance ...

Page 17

... Input Impedance Measurement Procedure The above block diagram shows the test procedure measur- ing the input impedance for the LMX2470. This applies to the FinRF, FinIF, and OSCin pins. The basic test procedure is to calibrate the network analyzer, ensure that the part is pow- ered up, and then measure the input impedance ...

Page 18

... POWER DOWN AND POWER UP MODES The power down state of the LMX2470 is controlled by many factors. The one factor that overrides all other factors is the EN pin. If this pin is low, this guarantees the part will be powered down ...

Page 19

Functional Description 1.4 DIGITAL LOCK DETECT OPERATION The RF PLL digital lock detect circuitry compares the differ- ence between the phase of the inputs of the phase detector generated delay of 10 nS. To enter the locked ...

Page 20

... PLL. 100 typical value. 1.6 FASTLOCK AND CYCLE SLIP REDUCTION The LMX2470 has enhanced features for Fastlock and cycle slip operation. The next several sections discuss the the benefits of using both of these features. There are four ...

Page 21

... If increasing the loop bandwidth during frequency acquisition is not sufficient to reduce cycle slip- ping, the LMX2470 also has a routine to decrease the com- parison frequency. Lock Time Multiplier x 2 ...

Page 22

Functional Description 1.6.4 RF PLL Fastlock Reference Table and Example The table below shows most of the trade-offs involved in choosing a steady-state charge pump current (RF_CPG), Parameter Advantages to Choosing Smaller RF_CPG 1. Allows capacitors in loop filter to ...

Page 23

... FRACTIONAL SPUR AND PHASE NOISE CONTROLS FOR THE LMX2470 The LMX2470 has several bits that have a large impact on fractional spurs. These bits also have a lesser effect on phase noise. The control words in question are CPUD[2:0], FM[1:0], and DITH[1:0 difficult to predict which settings ...

Page 24

... Control Register Content Map Because the LMX2470 registers are complicated, they are organized into two groups, basic and advanced. The first four registers are basic registers that contain critical information necessary for the PLL to achieve lock. The last 5 registers are for features that optimize spur, phase noise, and lock time performance ...

Page 25

25 www.national.com ...

Page 26

Programming Description 2.1 R0 REGISTER Note that this register has only one control bit. The reason for this is that it enables the N counter value to be changed with a single write statement to the PLL. REGISTER 23 22 ...

Page 27

Programming Description 2.2 R1 REGISTER REGISTER DATA[19:0] ( Except for the RF_N Register, which is [22: RF_PD 1 RF_R[5:0] 2.2.1 RF_FD[11: PLL Fractional Denominator The function of these bits are described in ...

Page 28

Programming Description 2.3 R2 REGISTER REGISTER DATA[19:0] ( Except for the RF_N Register, which is [22: IF_PD IF_P IF_CPG 2.3.1 IF_N[16: Divider Value The IF N divider is a classical dual modulus ...

Page 29

Programming Description 2.4 R3 REGISTER REGISTER DATA[19:0] ( Except for the RF_N Register, which is [22: RF_CPG[3:0] 2.4.1 IF_R[14: Divider Value For the IF R divider, the R value ...

Page 30

Programming Description 2.5 R4 REGISTER This register controls the conditions for the RF PLL in Fastlock. REGISTER DATA[19:0] ( Except for the RF_N Register, which is [22: CSR[1:0] RF_CPF[3:0] 2.5.1 RF_TOC -- RF ...

Page 31

Programming Description 2.5.3 RF_CSR[1: Cycle Slip Reduction CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence of phase detector cycle slips. Note that the Fastlock charge pump current, ...

Page 32

Programming Description 2.7 R6 REGISTER REGISTER DATA[19:0] ( Except for the RF_N Register, which is [22: RF_ CPT 2.7.1 MUX[3:0] Frequency Out & Lock Detect MUX These ...

Page 33

Programming Description 2.7.5 FM[1:0] -- Fractional Mode Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels closer to the carrier by pushing this noise to higher frequency offsets from the carrier. In general, the ...

Page 34

Programming Description 2.8 R7 REGISTER REGISTER RF_FD2[9:0] 2.8.1 Fractional Numerator Determination { RF_FN2[9:0], RF_FN[11:0], FDM } In the case that the FDM bit is 0, then the part operates in 12-bit fractional mode, and ...

Page 35

Programming Description 2.9 R8 REGISTER DITH [1:0] The R8 Register controls some additional bits that may be useful in optimizing phase noise, lock time, and spurs. 2.9.1 CPUD[2:0] -- ...

Page 36

... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted Ultra Thin Chip Scale Package (SLE) For Tape and Reel (2500 Units per Reel) Order Number LMX2470SLEX NS Package Number SLE24A 2. A critical component is any component of a life support device or system whose failure to perform ...

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