LMX2353 National Semiconductor Corporation, LMX2353 Datasheet
LMX2353
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LMX2353 Summary of contents
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... Serial data is transferred into the LMX2353 via a three wire interface (Data, LE, Clock). Supply voltage can range from 2 5.5 V. The LMX2353 fea- tures very low current consumption; typically 5 3.0V. The LMX2353 is available in a 16-pin TSSOP or a 16-pin CSP surface mount plastic package. ...
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... Connection Diagrams TOP VIEW Order Number LMX2353TM or LMX2353TMX See NS Package Number MTC16 Pin Description Pin No. Pin Name CSP TSSOP GND INB 5 6 GND 6 7 OSC CLK 10 11 DATA ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage Voltage on any pin with GND = Storage Temperature ...
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Electrical Characteristics All min/max specifications are guaranteed by design, or test, or statistical methods (Continued) Symbol Parameter MICROWIRE TIMING t Data to Clock Setup Time CS t Data to Clock Hold Time CH t Clock Pulse Width High CWH t ...
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Charge Pump Current Specification Definitions sink current CPo sink current CPo sink current CPo ...
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... Typical Performance Characteristics LMX2353 Charge Pump Current vs CP Voltage O CP_WORD = 0011 and 1111 LMX2353 V Voltage vs V Load Current in V Doubler Mode www.national.com I TRI-STATE vs CPO CP Voltage O DS101124-10 Sink vs Source Mismatch (See (Note 6) under Charge Pump Current Specification Definitions) ...
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... The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer such as the National Semiconductor LMX2353, a voltage controlled oscillator (VCO), and a passive loop filter. The frequency synthesizer includes a phase detector, current mode charge pump, as well as programmable reference [R] and feedback [N] frequency dividers ...
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... FEEDBACK DIVIDER (N-COUNTER) The N counter is clocked by the small signal f The integer part is configured as a 5-bit A counter and a 10-bit B counter. The LMX2353 is capable of operating from 500 MHz to 1.2 GHz with the 16/17 prescaler offering a continuous integer divide range from 272 to 16399, and 1.2 GHz to 2.5 GHz with the 32/33 prescaler offering a continuous integer divide range from 1056 to 32767 ...
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... Programming Description 2.1 MICROWIRE INTERFACE The LMX2353 register set can be accessed through the MICROWIRE interface. A 24-bit shift register is used as a temporary register to indirectly program the on-chip regis- ters. The shift register consists of a 24-bit DATA[21:0] field and a 2-bit ADDRESS[1:0] field as shown below ...
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Programming Description (Continued) 2.1.2 Registers’ Truth Table www.national.com 10 ...
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Programming Description 2.2 R REGISTER If the ADDRESS[1:0] field is set data is transferred from the 24-bit shift register into the R register which sets the PLL’ s 15-bit R-counter divide ratio when Latch Enable (LE) ...
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... The MICROWIRE control register remains active and capable of loading and latching in data during all of the power down modes. 2.3.2.3 Prescaler Modulus Select (PRESC_SEL) The PRESC_SEL bit is used to set the RF prescaler modulus value. The LMX2353 is capable of operating from 500 MHz to 1.2 GHz with the 16/17 prescaler, and 1.2 GHz to 2.5 GHz with the 32/33 prescaler selection. www.national.com ...
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Programming Description 2.3.2.4 Power Down Mode (PWDN_MODE) Synchronous Power Down Mode The PLL loop can be synchronously powered down by setting the PWDN mode bit HIGH (F2_19=1) and then asserting the power down mode bit (N20 = 1). The ...
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Programming Description R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767) P: Preset modulus of dual modulus prescaler ( 32) 2.4 F1 REGISTER If the ADDRESS[1:0] field is set ...
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Programming Description 2.4.2.3 Analog Lock Detect Filter When the F LD output is configured as analog lock detect output, an external lock detect circuit is needed in order to provide a O steady LOW signal when the PLL is ...
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Programming Description 2.4.2.4 Typical Lock Detecting Timing 2.5 F2 REGISTER If the ADDRESS[1:0] field is set data is transferred from the 24-bit shift register into the F2 register when Latch Enable (LE) signal goes high. The ...
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Programming Description The low gain or steadystate mode for fastlocking is defined to be whenever the charge pump current selected is less than 900 µA. The high gain or acquisition mode is defined to be whenever the charge pump ...
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... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted TSSOP Package For Tube Quantity (94 Units Per Tube) For Tape and Reel (2500 Units Per Reel) Order Number LMX2353TM or LMX2353TMX NS Package Number MTC16 18 ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted (Continued) Chip Scale Package For Tape and Reel (2500 Units Per Reel) Order Number: LMX2353SLBX NS Package Number SLB16A 2. A critical component is any component of a life support device or system whose failure to perform ...