LMX2301 National Semiconductor Corporation, LMX2301 Datasheet - Page 6

• Manufacturer Part Number: LMX2301
• Description: Pllatinumtm 160 Mhz Frequency Synthesizer For Rf Personal Communications
• Manufacturer: National Semiconductor Corporation

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Functional Description
The simplified block diagram below shows the 19-bit data register the 14-bit R Counter and the R15 Latch and the 11-bit
N Counter (intermediate latches are not shown) The data stream is clocked (on the rising edge) into the DATA input MSB first
If the Control Bit (last bit input) is HIGH the DATA is transferred into the R Counter (programmable reference divider) and the
S Latch (power up counter reset) If the Control Bit (LSB) is LOW the DATA is transferred into the N Counter (programmable
divider)
PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND COUNTER RESET (R15 LATCH)
If the Control Bit (last bit shifted into the Data Register) is HIGH data is transferred from the 19-bit shift register into a 14-bit
latch (which sets the 14-bit R Counter) and the 1-bit R15 Latch which can be used to force an immediate load of the R and N
counters during a cold power up condition Serial data format is shown below
SUGGESTED PROGRAMMING SEQUENCE AFTER COLD POWER-UP
1 Program N counter with desired divide ratio
2 Program R counter with R15
3 Program R counter with R15
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14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO
(R COUNTER)
Notes Divide ratios less than 3 are prohibited
Divide
16383
Ratio
R
3
4
#
Divide ratio 3 to 16383
R1 to R14 These bits select the divide ratio of the programmable
reference divider
C Control bit (set to HIGH level to load R counter and R15 Latch)
Data is shifted in MSB first
14
R
0
0
1
#
13
R
0
0
1
#
12
R
0
0
1
#
e
e
11
1 and desired divide ratio (N and R counters hold at load state )
0 and desired divide ratio (N and R counters start counting )
R
0
0
1
#
10
R R
0
0
1
#
9
0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 1 0 0
1 1 1 1 1 1 1 1 1
# # # # # # # # #
R
8
R
7
R
6
R
5
R
4
R
3
6
R
2
R
1
1-BIT COUNTER RESET
(R15 LATCH)
The 1-bit counter reset latch controls
whether the R and N counters are im-
mediately forced to load conditions
upon power up If R 15
N and R latch states are immediately
read into the respective counters
Remove
Forced Load
Force
Load State
Counter
Reset
TL W 12458 – 14
e
TL W 12458 – 1
HIGH the
15
R
0
1