STW8009 STMicroelectronics, STW8009 Datasheet
STW8009
Available stocks
Related parts for STW8009
STW8009 Summary of contents
Page 1
... The 27 MHz clock and the device power management are controlled through the digital processor interface [PORn, Suspend and 2-wire I2C compatible serial MPU]. This digital processor interface also controls the STw80x9 operating modes (off, sleep, standby and active). Rev 6 STw8009 STw8019 1/65 www.st.com 1 ...
Page 2
... TV/VCR plug insertion detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.12 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13.1 4.13.2 4.14 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 Register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 Description 5.2.1 5.2.2 6 Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 2 wire serial MPU control interface (I2C compatible 7-bit address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2/65 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Mode transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DENC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Control & power management unit registers . . . . . . . . . . . . . . . . . . . . . 45 STw8009/STw8019 ...
Page 3
... STw8009/STw8019 10 bits address mode 6.2 YcbCr bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.3 Electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9 Color test pattern waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1 TFBGA 49 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.2 VFBGA 49 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Contents ...
Page 4
... Power consumption/R load = 37.5 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 28. DAC & Video output characteristics / Rload = 37.5 ohm – MHz – Rext = 2.4 kohm 53 Table 29. TFBGA 4x4x1 Table 30. VFBGA 3x3x1 balls - Pitch 0.4 ball 0. Table 31. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 32. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4/65 Figure Figure STw8009/STw8019 ...
Page 5
... STw8009/STw8019 List of figures Figure 1. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. STw8009 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. STw8019 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Ball layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. Input data format (ITU-R656/D1 4:2: Figure 6. PAL-BDGHI, PAL-N typical VBI waveform, interlaced mode (ITU-R625 line numbering Figure 7. NTSC-M typical VBI waveforms, interlaced mode (SMTPE-524 line numbering . . . . . . . . 13 Figure 8 ...
Page 6
... Suspend and 2-wire I2C compatible serial MPU]. This digital processor interface also controls the operating modes (off, sleep, standby and active). Figure 1. Application diagram Naming convention Unless clearly specified in the document, STw80x9 stands for both STw8009 and STw8019. 6/65 STw80x9 C/CVBS Clk ...
Page 7
... STw8009/STw8019 2 Functional block diagram Figure 2. STw8009 block diagram Figure 3. STw8019 block diagram Functional block diagram 7/65 ...
Page 8
... Digital I/O 1.8V/2.8V Digital Input 1.8V/2.8V Digital input 1.8V/2.8V Digital input 1.8V/2.8V Digital input 1.8V/2.8V STw8009/STw8019 Description Digital core chip supply Digital core chip ground Digital I/O supply Digital I/O ground Digital I/O supply Digital I/O ground DAC2 matrix analog power supply DAC1 matrix analog power supply 2.8/3.3 V digital feature supply 2.8 /3.3 V digital feature supply ...
Page 9
... STw8009/STw8019 Table 1. Product name ball functions (continued) Ball Name A2 C/CVBS Analog output A6 Y Analog output B1 TDI B2 TDO Digital output C2 TCK C3 TMS D4 Test D3, F1, tst_ana[0: PlugDet Figure 4. Ball layout C/CVBS C/CVBS B B TDI TDI TDO TDO C C Vdd_IO1 Vdd_IO1 ...
Page 10
... Y=235dec. Similarly it defines 255 quantification levels for the color difference components (Cr, Cb) centered around 128. Accordingly, incoming YcbCr samples can be saturated. In this case STw80x9 provides a saturation limitation feature to avoid having heavily saturated signal before digital to analog conversion and to avoid generating a distorted signal at STw80x9 CVBS or Y/C outputs. 10/65 STw8009/STw8019 ...
Page 11
... STw8009/STw8019 4.5 Video timing The DENC outputs video in PAL-B,D,G,H,I, PAL-N, PAL-M or NTSC-J, M standards (‘NTSC- 4.43’ is also possible). The burst sequences are internally generated, subcarrier generation being performed numerically with PIX_CLK as reference. 4-frame bursts are generated for PAL or 2-frame bursts for NTSC. Rise and fall times of synchronization tips and burst envelope are internally controlled according to the relevant ITU-R and SMPTE recommendations ...
Page 12
... M) 128T 1728T 151T (145T in SECAM) 115T 1560T 131T 139T 1888T 169T reference). The normal burst always starts H STw8009/STw8019 1440T Digital active line 1440T Digital active line 1280T Digital active line 1536T Digital active line T = clock period PAL, NTSC: 37 ...
Page 13
... STw8009/STw8019 Figure 6. PAL-BDGHI, PAL-N typical VBI waveform, interlaced mode (ITU-R625 line numbering) 308 309 310 311 621 622 623 308 309 310 311 621 622 623 Frame synchronization reference V I, II, III and and and 7 th ...
Page 14
... III 524 525 261 262 263 264 265 I II III IV fields Horizontal blanking interval (bit aline = 0) c2 (bit aline = 1) STw8009/STw8019 Full VBI1 Full VBI2 266 267 268 269 270 266 267 268 ...
Page 15
... STw8009/STw8019 Table 2. NTSC and PAL timings NTSC-M 5.38 μs (even lines) (1) a 5.52 μs (odd lines) 1.56 μs b1 1.56 μs b2 8.8 μs c1 9.41 μ cycles of 3.58MHz 1. These are typical values. Actual values will depend on the static offset programmed for subcarrier generation 4.6 Sub-carrier generation A Direct Digital Frequency Synthesizer (DDFS) generates the required color sub-carrier frequency using a 24-bit phase accumulator ...
Page 16
... Functional description Figure 10. Luma filtering Figure 11. Luma filtering with 3.58 MHz trap 16/65 Amplitude (dB) Frequency (MHz) Frequency (MHz) STw8009/STw8019 ...
Page 17
... STw8009/STw8019 Figure 12. Luma filtering with 4.43 MHz trap 4.8 Chrominance encoding Chroma components are computed from demultiplexed Cb, Cr samples. Before modulating the subcarrier, the chroma components are band-limited and interpolated at pixel clock rate. A set of 4 different filters is available for chroma filtering to suit a wide variety of applications in the different standards and filters recommended by ITU-R 624-4 and SMPTE170-M. The available – ...
Page 18
... Functional description Figure 14. 1.3 MHz chroma filter Figure 15. 1.6 MHz chroma filter Figure 16. 1.9 MHz chroma filter 18/65 Frequency (MHz) Frequency (MHz) Frequency (MHz) STw8009/STw8019 ...
Page 19
... STw8009/STw8019 4.9 Composite video signal generation The composite video signal is created by adding the luminance and the chrominance components. A saturation function is included in the adder to avoid overflow errors. 4.10 Macrovision The chrominance luminance and composite video signals and RGB video signals can be altered according to the Macrovision This process is controlled via the I² ...
Page 20
... MPU interface. STw80x9 saves the register values. – The 27 MHz pixel clock is distributed in all STw80x9. The DACs are supplied by the 2.8 /3.3 V and can be individually activated or deactivated. For example only one DAC in CVBS output and both DACs in Y/C output. 20/65 STw8009/STw8019 ...
Page 21
... Active to Sleep mode and an internal Reset signal is generated by the Control Power Unit management to the DENC part. This signal has a 6 pixclk duration (pixclk = 27 MHz). All supplies are applied but STw8009 All supplies are applied but STw8009 suspend is asserted ...
Page 22
... At power up, supplies must be applied according to the following sequence: VddIO1, VddIO2 (1.8V/2.8V) then, Vdd (1.2V/1.4V) then, VccA1, VccA2, VccA3, VccA4 (2.8V/3.3V) and removed according to the following sequence: VccA1, VccA2, VccA3, VccA4 (2.8V/3.3V) then, Vdd (1.2V/1.4V) then, VddIO1, VddIO2 (1.8V/2.8V) 4.14 JTAG interface To ease the integration of STw80x9 in its system application, a JTAG interface is available. 22/65 STw8009/STw8019 ...
Page 23
... STw8009/STw8019 5 Control registers 5.1 Register addresses Table 3. Register addresses Name Type N° Bit7 DENC registers configuration0 R/W 00 std1 configuration1 R/W 01 configuration2 R/W 02 nintrl main_ configuration3 R/W 03 entrap configuration4 R/W 04 syncin_ad1 syncin_ad0 configuration5 R/W 05 selrst_inc configuration6 R/W 06 softreset configuration7 R/W 07 ph_rst_ configuration8 R/W 08 mode1 Status R 09 increment_dfs R/W 10 increment_dfs R/W 11 increment_dfs R/W 12 phase_dfs R/W 13 phase_dfs R/W 14 dac2mult ...
Page 24
... STw8009/STw8019 Bit3 Bit2 Bit1 c3(3) c3(2) c3(1) c4(3) c4(2) c4(1) c5(3) c5(2) c5(1) c6(3) c6(2) c6(1) c7(3) c7(2) c7(1) c8(3) c8(2) c8(1) xxx plg_div_y1 plg_div_y0 l0(3) l0(2) l0(1) l1(3) l1(2) l1(1) l2(3) l2(2) l2(1) l3(3) l3(2) l3(1) l4(3) l4(2) l4(1) l5(3) l5(2) l5(1) l6(3) l6(2) l6(1) l7(3) l7(2) l7(1) l8(3) l8(2) l8(1) l9(3) l9(2) l9(1) xxx main_if_del xxx [0] ennotch [0] [0] [0] [0] hue_cont hue_cont hue_cont (3) (2) (1) main_chr_ main_chr_ main_chr_ del3 del2 del1 ...
Page 25
... STw8009/STw8019 5.2 Description (*) = DEFAULT mode when not_reset pin is active (LOW level) Caution: All binary values quoted should be understood as MSB........LSB 5.2.1 DENC registers REGISTER 0 content default Table 4. std1, std0 std1 0 0 (*) Standard on hardware reset is NTSC; any standard modification selects automatically the right parameters for correct subcarrier generation ...
Page 26
... PAL filter -3dB high def. NTSC filter (ATSC compliant) & PAL f =1.6MHz -3dB M/N (ITU-R 624.4 compliant) high def. PAL filter: Rec 624 - 4 for PAL BDG/I f =1.9MHz -3dB compliant. STw8009/STw8019 Type: R/W setup_ coki main [0] Typical application [0] ...
Page 27
... STw8009/STw8019 setup_main : pedestal 0 = Blanking level and black level are identical on all lines. (e.g.: Argentinian PAL-N, Japan NTSC-M, PAL-BDGHI) (*) 1 = Black level is 7.5 IRE above blanking level on all lines outside VBI (e.g. Paraguayan and Uruguayan PAL-N). In all cases, gain factor is adjusted to obtain the required levels for chrominance. ...
Page 28
... Automatic reset of the oscillator every line 1 Automatic reset of the oscillator every 2 0 Automatic reset of the oscillator every 4 1 Automatic reset of the oscillator every 8 configuration3 Address: 0x0003 trap_4. [0] [0] STw8009/STw8019 selection nd field th field th field 180 , or 270 correction is Type: R/W ...
Page 29
... STw8009/STw8019 REGISTER 4 syncin_ content default syncin_ad[1:0] : Adjustment of incoming sync signals. Used to insure correct interpretation of incoming video samples when the encoder is slaved to incoming sync signals (inc. ‘F/H’ flags stripped off ITU-R656/D1 data). Table 8. syncin_ad[1:0] syncin_ad1 (*) syncout_ad[1:0] : Adjustment of outgoing sync signals. ...
Page 30
... Both fields of all the frames following the writing of this value x 1 are modified according to “lref” and “ltar” bits of registers 21- 22-23 (by default, “lref”=0 and “ltar”=1 which leads to normal mode above). STw8009/STw8019 Type: R/W [0] [0] [0] [0] Type: R/W ...
Page 31
... STw8009/STw8019 Table 10. jump, dec_ninc, free_jump jump Two lines are skipped (inserted) in 525/60 and four lines in 625/50 standards Note: bit “jump” is automatically reset after use. Table 11. cfc[1:0]: color frequency control via CFC line cfc1 (*) maxdyn : max dynamic magnitude allowed on YCrCb inputs for encoding. ...
Page 32
... Register6 cfc(1:0) bits. enabled - phase is reset following the detection of rst bit on cfc 1 line pix_clk after loading of cfc’s LSB. Address: 0x0009 hok atfr STw8009/STw8019 Type: R/W blk_all xxx xxx ...
Page 33
... STw8009/STw8019 fieldct[2:0] : Digital field identification number 000 = indicates field 1 ... 111 = indicates field 8 fieldct[0] also represents the odd/even information (odd=’0’, even=’1’) jump : indicates whether a frame length modification has been programmed at ‘1’ from programming of bit’ jump’ to end of frame(s) concerned. ...
Page 34
... The hard-wired values being out of any register, they cannot be read out. Reset values: D9C000hex for PAL BDGHI 1FC000hex for NTSC-M, 000000hex (blue lines) 34/65 Address: Phase_dfs 0x000D to 0x000E xxx xxx xxx xxx o21 o20 o19 o18 STw8009/STw8019 Type: R/W xxx xxx o23 o22 o17 o16 o15 o14 ...
Page 35
... STw8009/STw8019 REGISTER 17 dac2_ content default dac2_mult[5:0]: multiplying factor on dac2_c digital signal before the D/A converters with 0.78% step. Table 13. dac2_mult[5:0]: multiplying factor on dac2_c digital signal ... (*) 1 ... 1 REGISTERS 21, 22, 23 clig_i_reg = ltarg[8:0] and lref[8:0] register 21 register 22 register 23 These registers may be used to jump from a reference line (end of that line target line of the SAME FIELD ...
Page 36
... Brightness Address STw8009/STw8019 0x0041 Type: R/W xxx [0] 0 [0] factor value (c_mult) 0 1.000000 (1.000000 Dec.) 1 1.000001 (1.015625 Dec.) 0 1.000010 (1.031250 Dec.) 1 1.000011 (1.046875 Dec.) ... ... 1 1.001111 (1.234375 Dec.) 0x0045 Type: R ...
Page 37
... STw8009/STw8019 REGISTER 70 content default Adjustment of the relative difference between high and low intensity luminance values of the displayed image is made according to the following formula: Yin is the 8-bit input luminance, Yout is the result of ‘Contrast’ operation (still on 8 bits) This value is saturated at 235 (16) or 254 (1) according to register6 bit ‘maxdyn’, c: contrast (2’ ...
Page 38
... STw8009/STw8019 Type: R/W ...
Page 39
... STw8009/STw8019 chroma_main_coef4 = Actual value + 32; chroma_main_coef5 = Actual value + 32; chroma_main_coef6 = Actual value chroma_main_coef7 = Actual value chroma_main_coef8 = Actual value Default values: chroma_main_coef0[4:0] = 10001 chroma_main_coef1[5:0] = 100111 chroma_main_coef2[6:0] = 1010100 chroma_main_coef3[6:0] = 1000111 chroma_main_coef4[7:0] = 01011111 chroma_main_coef5[7:0] = 01110111 chroma_main_coef6[7:0] = 01101100 chroma_main_coef7[7:0] = 01111011 chroma_main_coef8[8:0] = 010000000 The FIR symmetrical filter has the following response: ...
Page 40
... STw8009/STw8019 0x0051 Type: R/W plg_div_ plg_div_ xxx flt_ys pix_clk ...
Page 41
... STw8009/STw8019 REGISTERS 82 to 91: Table 17. Luma_coef_[0:9] luma_coef_0 reg_82 xxx luma_coef_1 reg_83 l9(9) luma_coef_2 reg_84 l6(8) luma_coef_3 reg_85 l7(8) luma_coef_4 reg_86 l4(7) luma_coef_5 reg_87 l5(7) luma_coef_6 reg_88 l6(7) luma_coef_7 reg_89 l7(7) luma_coef_8 reg_90 l8(7) luma_coef_9 reg_91 l9(7) Values from these registers are used only when bit flt_ys of register 81 is set to 1. The coefficient values of luma_coef_0 to luma_coef_7 should be entered as 2’s complement, and the rest as normal positive values ...
Page 42
... Configuration 13 Address: dac12_ conf [0] [0] 0 dac1 Y Hue control Address: 0x0069 hue_ hue_ hue_con hue_ cont (6) t (5) cont ( STw8009/STw8019 0x005D Type: R/W main_if_ xxx xxx del [ 0x005E Type: R/W ennotch 0 [0] 0 [0] 0x005F Type: R/W [0] [0] [0] [0] dac2 C ...
Page 43
... STw8009/STw8019 hue_control [6:0] : absolute value of phase adjustment, range 1 to 127. LSB (0x01) implies 0.17578127 degrees, 0x7F imply 22.324 degrees hue_control [7] : Sign of phase 1 = +ve; (*) 0 = -ve (*) “00000000” “10000000” “11111111” “01111111” REGISTER 106 content default dac1_mult(5:0) : multiplying factor on dac1_y digital signal before the D/A converters with ...
Page 44
... Others 1 Others 0 + 0.5 pixel delay on chroma Chroma Delay Enable Address: 0x006D - - - - STw8009/STw8019 path encoding [One pixel corresponds to /fpix_clk] 0 pixel delay on chroma (reference delay) Type: R/W - [0] [0] main_chr _del_en 0 ...
Page 45
... STw8009/STw8019 5.2.2 Control & power management unit registers Control and power management unit REGISTER 128 content default standby : In this mode the analog subsystem is supplied by the 1.2V/1.4V and the 2.8V/3.3V, but the DACs are set in power down mode, via poff[1:2] bits (Reg 130 & 131). ...
Page 46
... LoadD : Reports Plugdet Ball status. Unless otherwise specified all voltages are referenced to GND Plugdet ball voltage less than VIL 1 = Plugdet ball voltage higher than VIH 46/65 DAC2 control Address Plugdet Address STw8009/STw8019 0x0083 Type: R/W pedestal poff2 notzerod2 Ond2 0x0084 Type: R LoadD - - - 0 ...
Page 47
... STw8009/STw8019 6 Bus interface 6.1 2 wire serial MPU control interface (I2C compatible) STw80x9 serial MPU control interface is compliant with I2C standard and acts only as a slave device. It supports 100 kHz and 400 kHz speeds. In addition to the basic definition of the I2C standard (SDA & SCL signals), STw80x9 serial MPU interface has an additional “ ...
Page 48
... Single transaction read r/w r STw8009 slave address STw8009 slave address A STw8009 register address A STw8009 register address Write (0) Write (0) S Start condition S Start condition Sr Repeated start condition Sr Repeated start condition 10 bits address mode In Write mode, several data can be sent without re-initializing a transfer, in this case, data is written in successive registers ...
Page 49
... STw8009 register address r/w r/w 8 LSBs 8 LSBs A2 A2 11110 11110 2MSBs 2MSBs Read (1) Read ( STw8009 register address A3 STw8009 register address 11110 11110 P P Stop condition A/NA Acknowledge / No Acknoledge Stop condition A/NA Acknowledge / No Acknoledge SU_DA Bus interface ...
Page 50
... Data input hold time ts Data input setup time Figure 22. Data bus timing CCIR data CLK27M ts: CCIR data to CLK27M setup time th: CCIR data to CLK27M hold time 50/65 Y0 Cr0 Y1 Cb2 Figure 22 ) Test conditions ts STw8009/STw8019 Y2 Cr2 Y3 Cb4 Min. Typ. Max 1.5 th Unit MHz % ns ns ...
Page 51
... STw8009/STw8019 7 Electrical characteristics 7.1 Absolute maximum rating Unless otherwise specified: T Table 23. Absolute maximum ratings Symbol Vdd Digital core supply voltage VddIO I/O digital supply voltage VccA Analog supply voltage VDCdig DC input voltage on any digital pin VDCana DC input voltage on any analog pin Pmax Maximum power dissipation ...
Page 52
... Min. All digital inputs All digital inputs 0.7*VddIO All digital outputs All digital outputs 0.8*VddIO All digital inputs / - < Vin < IL All digital inputs / -10 V VCCIO < Vin < IH STw8009/STw8019 ) Typ. Max. Unit 400 kHz ns ns 300 ns ns 300 ...
Page 53
... STw8009/STw8019 Table 27. Power consumption/R load = 37.5 ohm Symbol Parameter PSL Sleep mode on Vdd Vdd PST Stand by mode on Vdd Vdd PST Stand by mode on Vcca Vcca PAC Active mode on Vdd Vdd PAC Active mode on VddIO VddIO PAC0 Active mode on Vcca Vcca PAC1 Active mode on Vcca ...
Page 54
... L.P. filter L.P. filter Y Y Vdd VIO VccA Vdd VIO VccA Vdd VIO VccA Vdd VIO VccA Supply Supply Gnd Gnd STw8009/STw8019 TV set TV set Ω VCR VCR ESD ESD Protection Protection Only for S-VHS Only for S-VHS Ω ...
Page 55
... STw8009/STw8019 9 Color test pattern waveforms Figure 24. NTSC composite Color test pattern waveforms 55/65 ...
Page 56
... Color test pattern waveforms Figure 25. NTSC S-video 56/65 STw8009/STw8019 ...
Page 57
... STw8009/STw8019 Figure 26. PAL composite Color test pattern waveforms 57/65 ...
Page 58
... Color test pattern waveforms Figure 27. PAL S-video 58/65 STw8009/STw8019 ...
Page 59
... STw8009/STw8019 10 Package mechanical data 10.1 TFBGA 49 balls Table 29. TFBGA 4x4x1.2 mm Reference ddd eee fff Dimensions (mm) Min Typ 0.15 0.8 0.2 0.25 0.3 3.85 4.00 3.00 3.85 4.00 3.00 0.50 0.5 Package mechanical data Max 1.2 0.6 0.35 4.15 4.15 0.08 0.15 0.05 59/65 ...
Page 60
... Package mechanical data Figure 28. TFBGA 49 balls 1.2 mm body size 60/65 STw8009/STw8019 ...
Page 61
... STw8009/STw8019 10.2 VFBGA 49 balls Table 30. VFBGA 3x3x1 balls - Pitch 0.4 ball 0.25 Reference ( ( ddd (3) eee (4) fff 1. VFBGA stands for V ery thin profile F ine pitch B all G rid A rray. Very thin profile: 0.80mm<A<=1.00mm/Fine pitch: e<1.00mm The maximum total package height is calculated by the following methodology 2 ...
Page 62
... The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. 62/65 See Note Note: STw8009/STw8019 ...
Page 63
... STw8009/STw8019 11 Ordering information Table 31. Order codes Part number STW8009B27R/LF STW8019B27R/LF STW8009B27T/LF STW8019B27T/LF STW8009BS3R/LF STW8019BS3R/LF STW8009BS3T/LF STW8019BS3T/LF Package TFBGA49 4x4 Tray TFBGA49 4x4 Tray TFBGA49 4x4 Tape and reel TFBGA49 4x4 Tape and reel VFBGA49 3x3 Tray VFBGA49 3x3 Tray VFBGA49 3x3 ...
Page 64
... Reviewed the text in paragraph” transition from off mode to sleep mode” in Section 4.13.2: Mode transition diagram 5 Updated “sleep mode” paragraph in modes . Added Table 22 and 6 Updated Section 4.10: MacrovisionTM copy protection STw8009/STw8019 Changes . NTSC-J, M). . Chapter 11: . Table 23: Absolute maximum Table 28: DAC & Video output . . . Section 4.13.1: Operating ...
Page 65
... STw8009/STw8019 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...