IRS2168 International Rectifier Corp., IRS2168 Datasheet - Page 16

• Manufacturer Part Number: IRS2168
• Description: Advanced Pfc And Ballast Control Ic In A 16-lead Soic Package
• Manufacturer: International Rectifier Corp.

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loop speed for achieving high power factor and low THD.
The off-time of M
L
is detected by a secondary winding on LPFC that is
connected to the ZX pin through an external current
limiting resistor R
internal 2 V threshold (V
off-time.
below 1.7 V (V
current discharges to zero which signals the end of the
off-time and M
repeats itself indefinitely until the PFC section is disabled
due to a fault detected by the ballast section (Fault
Mode), an over-voltage or undervoltage condition on the
DC bus, or, the negative transition of ZX pin voltage does
not occur. Should the negative edge on the ZX pin not
occur, M
a turn-on of M
the voltage on the COMP pin. The watch-dog pulses
occur every 400 µs (t
positive- and negative-going signal is detected on the ZX
pin and normal PFC operation is resumed. Should the
OC pin exceed the 1.2 V (V
during the on-time, the PFC output will turn off.
circuit will then wait for a negative-going transition on the
ZX pin or a forced turn-on from the watch-dog timer to
turn the PFC output on again.
Figure 14: Inductor current, PFC pin, ZX pin and OC pin
timing diagram
COMP
VBUS
PFC
ZX
Figure 13: IRS2168D detailed PFC control circuit
current to discharge to zero. The zero current level
1
5
6
3.0V
PFC
PFC
5.1V
I
COMP2
OC
LPFC
ZX
4.0V
Run Mode Signal
1.2V
A negative-going edge on the ZX pin falling
GAIN
will remain off until the watch-dog timer forces
Discharge
2.0V
VCC to
UVLO-
PFC
PFC
OTA1
ZXTH+
PFC
ZX
for an on-time duration programmed by
is turned on again (Fig. 14). The cycle
COMP3
. A positive-going edge exceeding the
M1
C1
is determined by the time it takes the
4.3V
- V
M2
COMP5
ZXTH+
WD
ZXHYS
Fault Mode Signal
COMP4
. . .
. . .
. . .
. . .
) indefinitely until a correct
) signals the beginning of the
OCTH+
) will occur when the L
S
R1
R2 Q
) over-current threshold
Q
S
R Q
RS4
RS3
Q
WATCH
TIMER
DOG
VCC
1.2V
7
8
The
PFC
OC
PFC
On-time Modulation Circuit
A fixed on-time of M
input voltage produces a peak inductor current which
naturally follows the sinusoidal shape of the line input
voltage. The smoothed averaged line input current is in
phase with the line input voltage for high power factor but
the total harmonic distortion (THD), as well as the
individual higher harmonics, of the current can still be too
high. This is mostly due to cross-over distortion of the
line current near the zero-crossings of the line input
voltage. To achieve low harmonics that are acceptable to
international standard organizations and general market
requirements, an additional on-time modulation circuit has
been added to the PFC control. This circuit dynamically
increases the on-time of M
nears the zero-crossings (Fig. 15). This causes the peak
L
current, to increase slightly higher near the zero-
crossings of the line input voltage. This reduces the
amount of cross-over distortion in the line input current
which reduces the THD and higher harmonics to low
levels.
Figure 15: On-time modulation circuit timing diagram
DC Bus Over-voltage Protection
Should over-voltage occur on the DC bus and the VBUS
pin exceeds the internal 4.3 V threshold (V
PFC output is disabled (set to a logic ‘low’). When the
DC bus decreases again and the V
below the internal 4.15 V threshold (V
pulse is forced on the PFC pin and normal PFC operation
is resumed.
DC Bus Undervoltage Reset
When the input line voltage decreases, the on-time of
M
time will continue to increase as the line voltage
continues to decrease until the OC pin exceeds the
internal 1.2 V over-current threshold (V
time, the on-time can no longer increase and the PFC can
no longer supply enough current to keep the DC bus fixed
for the given load power. This will cause the DC bus to
begin to decrease. The decreasing DC bus will cause the
V
(V
PFC
BUS
PFC
BUSUV-
I
PFC
LPFC
pin
pin to decrease below the internal 3.0 V threshold
current, and therefore the smoothed line input
increases to keep the DC bus constant. The on-
0
0
) (Fig. 12).
near peak region of
rectified AC line
PFC
over an entire cycle of the line
PFC
as the line input voltage
IRS2168D(S)PbF
near zero-crossing region
BUSOV-
BUS
of rectified AC line
OCTH+
pin decreases
), a watch-dog
BUSOV+
).
At this
), the
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