S6B0708 Samsung Semiconductor, Inc., S6B0708 Datasheet
S6B0708
Related parts for S6B0708
S6B0708 Summary of contents
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... GRAPHIC DRIVER FOR DOT MATRIX LCD INTRODUCTION S6B0708 is a single-chip LCD driver IC for liquid crystal dot-matrix graphic display systems. It incorporates 192 driver circuit for 64 common and 128 segment and 64 x 128-bit bit-map RAM capable of interfacing with the microprocessor, accepting 8-bit parallel display data directly from it, and storing data in an one chip display data RAM ...
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... S6B0708 LCD BLOCK DIAGRAM C1 ... C32 S1 S2 ... VDD Channel V3 Common V4 V5 32bit Shift VEE Reg VSS FS Display Timing Generator Circuit C Oscillator CR R ADC 2 64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX ... S63 S64 S65 S66 ... 64 Channel Segment Driver 64-Bit Data Latch 64-Bit Data Latch ...
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... GRAPHIC DRIVER FOR DOT MATRIX LCD PAD CONFIGURATION 219 S6B0708 250 Item Chip size Pad pitch Bumped pad size Bumped pad height S6B0708 Y ( Pad No. Size X - 12590 - 90 (min 140 86 - 218 56 219 - 250 140 All Pad 17 (typ ...
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... S6B0708 LCD PAD CENTER COORDINA TES Pad No. Pad Coordinate Name X 1 Dummy -6115 -1600 2 Dummy -6025 -1600 3 Dummy -5935 -1600 4 VEE -5477 -1600 5 VEE -5257 -1600 6 VEE -5037 -1600 7 V5 -4817 -1600 8 V5 -4597 -1600 9 V5 -4377 -1600 10 V4 -4157 -1600 ...
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... S43 1935 1635 131 S44 1845 1635 132 S45 1755 1635 133 S46 1665 1635 134 S47 1575 1635 S6B0708 Pad Pad Coordinate No. Name Y X 135 S48 1485 136 S49 1395 137 S50 1305 138 S51 1215 139 S52 ...
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... S6B0708 LCD Table 1. Pad Center Coordinates (Continued) Pad Pad Coordinate No. Name X 201 S114 -4455 1635 202 S115 -4545 1635 203 S116 -4635 1635 204 S117 -4725 1635 205 S118 -4815 1635 206 S119 -4905 1635 207 S120 -4995 1635 208 S121 ...
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... Power supply. connect to MPU power supply pin VCC Ground For LCD driver circuit LCD driver supply voltages The voltages must satisfy the following relationship VDD Description S6B0708 S6B0708 R Open FS Oscillation Frequency H Fosc = 430kHz L Fosc = 215kHz Description VEE C ...
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... S6B0708 LCD MICROPROCESSOR INTERFACE Name I/O Type CS1B I First chip(S1 ~ S64) select input. Data input/output is enabled via E, RS, RW, and DB[0:7]when CS1B = Low. CS2B I Second chip(S65 ~ S128) select input. Data input/output is enabled via E, RS, RW, and DB[0:7] when CS2B = Low Register selection Read or write E Enable signal ...
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... I Address control signal of Y address counter. ADC H L SHL I Selection of data shift direction SHL H L S6B0708 Description Description Phase of Internal Shift Clock (CLK2) H Data shift at the rising edge of CLK2 L Data shift at the falling edge of CLK2 Segment Output Direction S1 S2 ..... S63 S65 S66 ...
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... FUNCTIONAL DESCRIPTI O N CHIP SELECT INPUT The S6B0708 has two chip select pins, CS1B and CS2B. It can interface with a microprocessor when these pins (CS1B or CS2B) are low. When both of these pins are set to high, DB0 to DB7 are at high impedance and RS, RW, and E inputs are disabled ...
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... GRAPHIC DRIVER FOR DOT MATRIX LCD BUSY FLAG Busy flag indicates whether S6B0708 is operating or not. When it is high, S6B0708 is in internal operation. When it is low, S6B0708 can accept the data or instruction. DB7 indicates busy flag of the S6B0708 DISPLAY TIMING GENER ATOR CIRCUIT This section explains how the timing generation circuit operates ...
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... S6B0708 LCD DISPLAY DATA RAM (DD RAM) The display data RAM stores pixel data for the LCD 128-column x 64-row addressable array as shown in Table 4. The 64 rows are divided into 8 pages of 8 lines. Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The microprocessor reads data from and writes data to RAM through the I/O buffer. ...
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... S6B0708 Table 4. Display Data RAM Data Bus (S1-S64) S63 S64 S65 S66 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 ...
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... S6B0708 LCD Page Line Segment Output Address Address 101 110 111 ADC Column Address Chip Select (CS1B) 14 64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX Table 4. Display Data RAM (Continued) ...
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... RW E DB[7:0] N Internal Signal WR Input Buffer Column Address Preset Page Address Set page address => K RAM MPU Signal DB[7:0] Internal Signal WR RD Output Buffer Column Address Preset Page Address Set page address S6B0708 D(N) D(N+1) D(N+2) N D(N) D(N+1) N N+1 N+2 N D(N) D(N+1) Figure 3. Write Timing N Dummy D(N) Dummy D(N) D(N+1) N N+1 N Figure 4. Read Timing ...
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... LCD DATA TRANSFER To match the timing of the display data RAM and registering to that of the controlling microprocessor, S6B0708 uses an internal data bus and bus buffer. When the microprocessor reads the contents of display data RAM, the data for the initial read cycle is first stored in the bus buffer (dummy read cycle). On the next read cycle, the data is read from the bus buffer onto the microprocessor bus ...
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... While RESETB is in low level, no instruction except status read can be accepted. Reset status appears at DB4. Refers to read status of "instruction description" The conditions of power supply at initial power up are shown in table 5. Item Reset time Rise time S6B0708 Common Output Table 5. Power supply initial conditions. ...
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... S6B0708 LCD INSTRUCTION DESCRIPTION Instruction DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read 1 1 display data Write 1 0 display data 0 1 busy 0 Status read Set column address Set display start line Set page address ...
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... Indicates whether the display off. When low, the display is on. When high, the display is off. This is the opposite of Display ON/OFF instruction. RESET Indicates the initialization is in progress by RESETB signal. When low, the chip is in active. When high, the chip is being reset. S6B0708 DB6 DB5 DB4 Read Data ...
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... S6B0708 LCD Set Page Address Sets the page address of display RAM from the microprocessor into the page address register. Along with column address register, Page address register assigns the address of the display RAM to be written to or read from display data. Changing the address doesn’t affect the display status. ...
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... Display ON / OFF Turns the display ON or OFF DB7 Display Display OFF S6B0708 DB6 DB5 DB4 DB6 DB5 DB4 ...
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... S6B0708 LCD ELECTRICAL SPECIFICA TIONS ABSOLUTE MAXIMUM RAT INGS Parameter Operating voltage Supply voltage Driver supply voltage NOTES: 1. Based on Vss = 0V 2. VLCD = VDD - VEE 3. Applies to SHL, FS, PCLK2, CR, RESETB, ADC, CS1B, CS2B, E, RW, RS and DB0 - DB7. 4. Voltage level VDD V0 V1 TEMPERATURE CHARACTE RISTICS ...
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... DB0 - DB7 at high impedance 6. V0, V1, V2, V3, V4 20pF 47k , fose = 450kHz, DB0 - DB7 = VDD, output = No load 8. External clock = 430kHz, RAM access cycle = 1MHz 5V 3.2V 1.4V -8.4V -10.2V -12V C64 10 5V 3.2V 1.4V -8.4V -10.2V -12V S128 S6B0708 Condition - DD - IH1 - IH2 - IL1 ...
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... S6B0708 LCD AC Characteristics (VDD = 4.5 to 5.5V -30 to +85 C) Mode Write mode E cycle time (refer to figure 6) E rise/fall time E pulse width high RW and RS setup time RW and RS hold time Data setup time Data hold time Read mode E cycle time (refer to figure 7) E rise/fall time ...
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... GRAPHIC DRIVER FOR DOT MATRIX LCD RS R/W E DB0 - DB7 S6B0708 V IH1 V IL1 IH1 t PWH V V IH1 IH1 V V IL1 IL1 OH1 Valid Data V OL1 t Figure 7. Read Mode Timing Diagram IH1 IL1 OH1 V OL1 ...
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... S6B0708 LCD APPLICATION DIAGRAM 1 (ADC = H, SHL = COM32 64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX .... SEG127 SEG128 S127 S128 (Bottom view ...
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... C64 . . . C33 Note: When ADC=L, connects chip select pins (CS1B, CS2B) as follows. - CS1B (MPU) -> CS2B (S6B0708) - CS2B (MPU) -> CS1B (S6B0708) S6B0708 SEG2 .... S128 S127 . ...
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... C 64 COM1 . . Note: When ADC=L, connects chip select pins (CS1B, CS2B) as follows. - CS1B (MPU) -> CS2B (S6B0708) - CS2B (MPU) -> CS1B (S6B0708) 28 64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX ttom view) S128 ...
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... GRAPHIC DRIVER FOR DOT MATRIX LCD APPLICATION DIAGRAM 4 (ADC = H, SHL = C32 S6B0708 ...