M50FLW040B ST Microelectronics, M50FLW040B Datasheet
M50FLW040B
Available stocks
Related parts for M50FLW040B
M50FLW040B Summary of contents
Page 1
... Figure 1. Packages PLCC32 (K) TSOP32 (NB 14mm TSOP40 ( 20mm PROGRAM/ERASE SUSPEND – Read other Blocks/Sectors during Program Suspend – Program other Blocks/Sectors during Erase Suspend ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code (M50FLW040A): 08h – Device Code (M50FLW040B): 28h 1/52 ...
Page 2
... Table 1. Signal Names (FWH/LPC Interface Table 2. Signal Names (A/A Mux Interface Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Addresses (M50FLW040A Table 4. Addresses (M50FLW040B SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 10 Input/Output Communications (FWH0/LAD0-FWH3/LAD3 Input Communication Frame (FWH4/LFRAME Identification Inputs (ID0-ID3 General Purpose Inputs (GPI0-GPI4) ...
Page 3
... Table 13. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program/Erase Controller Status (Bit SR7 Erase Suspend Status (Bit SR6 Erase Status (Bit SR5 Program Status (Bit SR4 Status (Bit SR3 Program Suspend Status (Bit SR2 Block Protection Status (Bit SR1 Reserved (Bit SR0 M50FLW040A, M50FLW040B 3/52 ...
Page 4
... M50FLW040A, M50FLW040B Table 14. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS . . . 24 Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 15. Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 16. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 17. General Purpose Inputs Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register . . . . . . . . . . . . . . 25 Manufacturer Code Register ...
Page 5
... Table 33. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 APPENDIX A.BLOCK AND SECTOR ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 34. M50FLW040A Block and Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 35. M50FLW040B Block and Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 APPENDIX B.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 23.Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only Figure 24 ...
Page 6
... M50FLW040A, M50FLW040B SUMMARY DESCRIPTION The M50FLW040 Mbit (512Kb x8) non-vola- tile memory that can be read, erased and repro- grammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines, an optional 12V power supply can be used to reduce the erasing and programming time ...
Page 7
... Table 2. Signal Names (A/A Mux Interface A0-A10 DQ0-DQ7 8 G DQ0-DQ7 AI08418B M50FLW040A, M50FLW040B FWH0/LAD0- Input/Output Communications FWH3/LAD3 FWH4/ Input Communication Frame LFRAME ID0-ID3 Identification Inputs GPI0-GPI4 General Purpose Inputs IC Interface Configuration RP Interface Reset INIT CPU Reset CLK ...
Page 8
... M50FLW040A, M50FLW040B Figure 4. PLCC Connections A/A Mux DQ0 A/A Mux Note: Pins 27 and 28 are not internally connected. Figure 5. TSOP32 Connections A10 8/ GPI1 GPI0 WP TBL M50FLW040A ID3/RFU 9 M50FLW040B ID2 ...
Page 9
... FWH3/LAD3 DQ3 FWH2/LAD2 DQ2 FWH1/LAD1 DQ1 FWH0/LAD0 DQ0 ID0 A0 ID1 A1 ID2 A2 ID3/RFU A3 AI08420B Addresses (M50FLW040B) Address Range Sector Size (KByte) 70000h-7FFFFh 16 x 4KBytes 60000h- 6FFFFh 50000h- 5FFFFh 40000h- 4FFFFh 5 x 64KBytes 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 16 x 4KBytes 00000h-0FFFFh 16 x 4KBytes 9/52 ...
Page 10
... M50FLW040A, M50FLW040B SIGNAL DESCRIPTIONS There are two distinct bus interfaces available on this device. The active interface is selected before power-up, or during Reset, using the Interface Configuration Pin, IC. The signals for each interface are discussed in the Firmware Hub/Low Pin Count (FWH/LPC) Signal ...
Page 11
... Erase operations are used. Any other voltage input to V ior, and should not be used hours during the life of the memory. Row/ V age measurements. M50FLW040A, M50FLW040B , the memory is ready for any read, program or OH Supply Voltage. The This is to prevent Bus Write operations from LKO ...
Page 12
... M50FLW040A, M50FLW040B Table 5. Memory Identification Input Configuration (LPC mode) Memory Number 1 (Boot memory BUS OPERATIONS The two interfaces, A/A Mux and FWH/LPC, sup- port similar operations, but with different bus sig- nals and timings. The Firmware Hub/Low Pin ...
Page 13
... Reset mode when RP is Low held Low, V during a Program or Erase operation, the opera- tion is aborted, and the affected memory cells no longer contain valid data. The memory can take PLRH M50FLW040A, M50FLW040B , and Output IH . The Data Inputs/Outputs will IL Figure 17., and Table ...
Page 14
... M50FLW040A, M50FLW040B Table 6. FWH Bus Read Field Definitions Clock Clock Cycle Cycle Field Number Count 1 1 START 2 1 IDSEL 3-9 7 ADDR 10 1 MSIZE 11 1 TAR 12 1 TAR 13-14 2 WSYNC 15 1 RSYNC 16-17 M=2n DATA previous 1 TAR +1 previous 1 TAR +1 Figure 7. FWH Bus Read Waveforms CLK ...
Page 15
... The FWH Flash Memory drives FWH0-FWH3 to 1111b, 1111b O indicating a turnaround cycle. 1111b The FWH Flash Memory floats its outputs and the host takes N/A (float) control of FWH0-FWH3. START IDSEL ADDR MSIZE M50FLW040A, M50FLW040B Description DATA TAR SYNC TAR Table AI08434B 15/52 ...
Page 16
... M50FLW040A, M50FLW040B Table 8. LPC Bus Read Field Definitions (1-Byte) Clock Clock Cycle Cycle Number Count 1 1 START CYCTYPE 13-14 2 WSYNC 15 1 RSYNC 16- Figure 9. LPC Bus Read Waveforms (1-Byte) CLK LFRAME LAD0-LAD3 Number of clock cycles 16/52 LAD0- ...
Page 17
... M50FLW040A, M50FLW040B Description Table 5. DATA TAR SYNC TAR Don't Care Data Output PPH Don't Care Don't Care shows the AI04430 DQ7-DQ0 Data Input ...
Page 18
... M50FLW040A, M50FLW040B COMMAND INTERFACE All Bus Write operations to the device are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings, and verifies the correct execution of the Program and Erase commands. The Pro- ...
Page 19
... During the Block Erase operation the memory will only accept the Read Status Register and Pro- gram/Erase Suspend commands. All other com- mands are ignored. M50FLW040A, M50FLW040B 23., for a suggested flowchart on using Table 18.. PP 26., for a suggested flowchart on using Table 18 ...
Page 20
... M50FLW040A, M50FLW040B See Figure 27., for a suggested flowchart on using the Block Erase command. Typical Block Erase times are given in Table Sector Erase Command. The command is used to erase a Uniform 4-KByte Sec- tor, setting all of the bits to ‘1’. All previous data in the sector are lost. ...
Page 21
... X 10h X 20h BA D0h X 32h SA D0h X 50h X B0h X D0h X 00h X 01h X 60h X 2Fh X C0h Table 5. M50FLW040A, M50FLW040B (1) 3rd 4th Addr Data Addr Data (Read (Read (Read (Read Addr2) Data2) Addr3) Data3) (Status (Status (X) (X) Reg) Reg) (Sig (Signat (Sig (Signat Addr) ure) ...
Page 22
... M50FLW040A, M50FLW040B STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operation. The bits in the Status Register convey specific in- formation about the progress of the operation. To read the Status Register, the Read Status Reg- ister command can be issued. The Status Register is automatically read after Program, Erase and Program/Erase Resume commands are issued ...
Page 23
... Block Using the A/A Mux Interface, the Block Protection Status bit is always ‘0’. Reserved (Bit SR0). Bit 0 of the Status Register is reserved. Its value should be masked. Error M50FLW040A, M50FLW040B SR7 SR6 SR5 SR4 SR3 (1) ‘0’ ...
Page 24
... M50FLW040A, M50FLW040B FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS When the Firmware Hub Interface/Low Pin Count is selected, several additional registers can be ac- cessed. These registers control the protection sta- tus of the Blocks, read the General Purpose Input pins and identify the memory using the manufac- turer code ...
Page 25
... Purpose Input pins should remain constant throughout the whole Bus Read cycle. Manufacturer Code Register Reading the Manufacturer Code Register returns the value 20h, which is the Manufacturer Code for STMicroelectronics. This register is read-only. Writing to it has no effect. M50FLW040A, M50FLW040B (1) Function (1) Function 25/52 ...
Page 26
... M50FLW040A, M50FLW040B PROGRAM AND ERASE TIMES The Program and Erase times are shown in 18.. Table 18. Program and Erase Times Parameter Byte Program Double Byte Program Quadruple Byte Program Block Program (2) Sector Erase (4 KBytes) Block Erase (64 KBytes) Chip Erase Program/Erase Suspend to Program pause ...
Page 27
... Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter R2=500 ) M50FLW040A, M50FLW040B Min. Max. Unit –65 150 °C 1 °C See note –0. ...
Page 28
... M50FLW040A, M50FLW040B DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Table 20. Operating Conditions Symbol V Supply Voltage ...
Page 29
... Note: 1. Sampled only, not 100% tested. 2. See PCI Specification 25° 1MHz DEVICE UNDER TEST 0.1µF 0.1µ includes JIG capacitance Test Condition M50FLW040A, M50FLW040B 1.5V AI01417 16. 16.7k AI08430 Min Max Unit 29/52 ...
Page 30
... M50FLW040A, M50FLW040B Table 24. DC Characteristics Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V (INIT) INIT Input High Voltage IH V (INIT) INIT Input Low Voltage IL (2) Input Leakage Current I LI IC, IDx Input Leakage I LI2 Current IC, IDx Input Pull Low ...
Page 31
... CLK Slew Rate Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification. tCYC tHIGH Test Condition (1) peak to peak M50FLW040A, M50FLW040B tLOW 0 p-to-p (minimum) AI03403 Value Min 30 ...
Page 32
... M50FLW040A, M50FLW040B Figure 15. FWH/LPC Interface AC Signal Timing Waveforms CLK FWH0-FWH3/ LAD0-LAD3 tCHFH tFLCH FWH4 START CYCLE Table 26. FWH/LPC Interface AC Signal Timing Characteristics PCI Symbol Symbol t t CHQV val ( CHQX t t CHQZ off t AVCH DVCH t CHAX CHDX ...
Page 33
... Enable Low PHGL Note: 1. See Chapter 4 of the PCI Specification. tPLPH tPLRH Test Condition Program/Erase Inactive Program/Erase Active (1) Rising edge only FWH/LPC Interface only A/A Mux Interface only M50FLW040A, M50FLW040B tPHWL, tPHGL, tPHFL ai08422 Value Min 100 Max 100 Max 30 Min 50 Min ...
Page 34
... M50FLW040A, M50FLW040B Figure 17. A/A Mux Interface Read AC Waveforms A0-A10 ROW ADDR VALID tAVCL RC G DQ0-DQ7 W RP Table 28. A/A Mux Interface Read AC Characteristics Symbol t Read Cycle Time AVAV t Row Address Valid to RC Low AVCL t RC Low to Row Address Transition CLAX t Column Address Valid to RC high ...
Page 35
... tCLAX tAVCH tAVCL tCHAX tWHWL tCHWH tVPHWH tWHRL tDVWH D IN1 D IN2 Parameter Low PP < 3.6V). PP M50FLW040A, M50FLW040B Read Status Ready to write Register Data another command tWHGL tQVVPL tWHDX VALID SRD Test Condition Value Min 100 Min 50 Min 5 Min 50 Min ...
Page 36
... M50FLW040A, M50FLW040B PACKAGE MECHANICAL Figure 19. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline Note: Drawing is not to scale. 36/ 0.51 (.020 1.14 (.045 PLCC-A ...
Page 37
... M50FLW040A, M50FLW040B inches Typ Min 0.125 0.140 0.060 0.095 0.015 0.013 0.021 0.026 0.032 0.004 0.485 0.495 0.447 0.453 0.188 0.223 0.300 – 0.585 0.595 0.547 0.553 0.238 0.273 0.400 – 0.050 – ...
Page 38
... M50FLW040A, M50FLW040B Figure 20. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline 1 N/2 TSOP-a Note: Drawing is not to scale. Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data Symbol Typ 0.500 38/ ...
Page 39
... DIE C millimeters Min Max 1.200 0.050 0.150 0.950 1.050 0.170 0.270 0.100 0.210 0.100 19.800 20.200 18.300 18.500 – – 9.900 10.100 0.500 0.700 0 5 M50FLW040A, M50FLW040B inches Typ Min Max – ...
Page 40
... M50FLW040A, M50FLW040B PART NUMBERING Table 33. Ordering Information Scheme Example:M50FLW040 Device Type M50 = Flash Memory for PC BIOS Architecture FL = Firmware Hub/Low Pin Count Interface Operating Voltage 3.0 to 3.6V CC Device Function 040 = 4 Mbit (x8), Uniform Blocks and Sectors Array Matrix 4KByte top sectors + 4KByte bottom sectors ...
Page 41
... FBF0002 M50FLW040A, M50FLW040B Block Sector Address Size No and Size Range Type (KByte) 6F000h- 4 6FFFFh 6E000h- 4 6EFFFh 6D000h- 4 6DFFFh 6C000h- 4 6CFFFh 6B000h- 4 6BFFFh 6A000h- 4 6AFFFh 69000h- 4 69FFFh ...
Page 42
... Note: In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0, and the re- maining address bits should be set according to the rules shown in the ADDR field of 42/52 Table 35. M50FLW040B Block Sector Sector Register Addresses Size No Address ...
Page 43
... FB90002 Note: In LPC mode, a most significant nibble, F, must be added to M50FLW040A, M50FLW040B Block Sector Address Size No and Size Range Type (KByte) 0F000h- 4 0FFFFh 0E000h- 4 0EFFFh 0D000h- 4 0DFFFh 0C000h- 4 0CFFFh 0B000h- 4 0BFFFh ...
Page 44
... M50FLW040A, M50FLW040B APPENDIX B. FLOWCHARTS AND PSEUDO CODES Figure 22. Program Flowchart and Pseudo Code Start Write 40h or 10h Write Address and Data Read Status Register SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES FWH/LPC Interface SR1 = 0 Only YES End Note Status check of SR1 (Protected Block), SR3 (V by following the correct command sequence ...
Page 45
... Program to Protected Block Error (1, 2) Invalid) and SR4 (Program Error) can be made after each program operation by following the correct PP M50FLW040A, M50FLW040B Double/Quadruple Byte Program command: – write 40h or 10h – write Start Address and 2/4 Data Bytes (3) (memory enters read status state after ...
Page 46
... M50FLW040A, M50FLW040B Figure 24. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) Start Write 30h Write Address 1 & Data 1 (3) Write Address 2 & Data 2 (3) Write Address 3 & Data 3 (3) Write Address 4 & Data 4 (3) Read Status Register SR7 = 1 ...
Page 47
... Note error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used Program Complete Write FFh Read Data M50FLW040A, M50FLW040B Program/Erase Suspend command: – write B0h – write 70h do: – read Status Register while SR7 = 0 ...
Page 48
... M50FLW040A, M50FLW040B Figure 26. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) Start Write 80h Write 10h Read Status Register SR7 = 1 YES SR3 = 0 YES SR4, SR5 = 0 YES SR5 = 0 YES End Note error is found, the Status Register must be cleared before further Program/Erase Controller operations. ...
Page 49
... NO Command Sequence Error (1) NO Erase Error (1) NO Erase to Protected Block Error (1) M50FLW040A, M50FLW040B Block Erase command: – Write 20h/32h – Write block Address and D0h (memory enters read Status Register after the Block Erase command) do: – Read Status Register – If SR7=0 and a Program/Erase Suspend command has been executed – ...
Page 50
... M50FLW040A, M50FLW040B Figure 28. Erase Suspend and Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register SR7 = 1 YES SR6 = 1 YES Read data from another block/sector or Program Write D0h Erase Continues 50/ Erase Complete Write FFh Read Data Program/Erase Suspend command: – ...
Page 51
... V (INIT) min parameter modified in IH Document status promoted from Target Specification to Product Preview Document renamed to M50FLW040A, M50FLW040B Block types removed from the Block and Sector Address tables Document promoted to Preliminary Data Wording in the textual discriptions revised throughout the document. TSOP32 package added. Updates to Tables 8, 9, 12, 13, 14, 15, 19, 26, ...
Page 52
... M50FLW040A, M50FLW040B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...