P1014AP ON Semiconductor, P1014AP Datasheet - Page 11

• Manufacturer Part Number: P1014AP
• Description: Search -----> NCP1014AP
• Manufacturer: ON Semiconductor

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is expressed by:
the IC actually pulses is given by
Finally,
using the same formula topology:
From these three definitions, the burst duty−cycle
can be computed:
equation with values extracted from the parameter section
gives a typical duty−cycle of 13%, precluding any lethal
thermal runaway while in a fault condition.
DSS Internal Dissipation
drain pin. In Flyback−based converters, this drain level can
easily go above 600 V peak and thus increase the stress on the
DSS startup source. However, the drain voltage evolves with
time and its period is small compared to that of the DSS. As
a result, the averaged dissipation, excluding capacitive losses,
can be derived by:
Figure 17 portrays a typical drain−ground waveshape where
leakage effects have been removed.
dc +
The rising slope from the latch−off level up to 8.5 V
The Dynamic Self−Supplied pulls energy out from the
ICC1 ·
the
ICC1
DV2
DV2
Tstart + DV1 · C
latch−off
)
P DSS + ICC1 · t Vds(t) u .
DV1
IC1
dc +
)
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
ICC2
DV3
Tstart ) Tsw ) TLatch
IC1
Figure 16. NCP101X Facing a Fault Condition (Vin = 150 Vdc)
time
Tstart
(eq. 3)
. The time during which
Tsw
can
TLatch + DV3 · C
.
Tsw
tsw + DV2 · C
Feeding
be
derived
ICC2
ICC1
(eq. 2)
(eq. 4)
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the
TLatch
.
.
.
.
11
derived by additive square area calculation:
toff can be expressed by:
can be evaluated by:
1 V Ripple
By looking at Figure 17, the average result can easily be
By developing Equation 5, we obtain:
Vds(t)
Figure 17. A typical drain−ground waveshape
where leakage effects are not accounted for.
Latch−off
t Vds(t) u+ Vin * Vin · ton
Vin
Level
t Vds(t) u+ Vin · (1 * d) ) Vr · toff
ton
Vr
Tsw
ton + Ip ·
toff
toff + Ip ·
dt
Vin
Lp
Tsw
(eq. 8)
Lp
Vr
) Vr · toff
(eq. 7)
.
Tsw
Tsw
where ton
(eq. 5)
(eq. 6)
t