P1014AP ON Semiconductor, P1014AP Datasheet - Page 16

• Manufacturer Part Number: P1014AP
• Description: Search -----> NCP1014AP
• Manufacturer: ON Semiconductor

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Full Latching Shutdown
when an abnormal situation is detected (overtemperature
or overvoltage). This feature can easily be implemented
through two external transistors wired as a discrete SCR.
When the OVP level exceeds the Zener breakdown
current flowing through Rhold should be small enough to let
the V
is fired. The NPN base can also receive a signal from a
temperature sensor. Typical bipolars can be MMBT2222
and MMBT2907 for the discrete latch. The MMBT3946
features two bipolars NPN+PNP in the same package and
could also be used.
Power Dissipation and Heatsinking
current−source (when active) and the MOSFET. Thus,
Ptot = P
surrounded by copper, it becomes possible to drop its
thermal resistance junction−to−ambient, R
to 75 C/W and thus dissipate more power. The
Other applications require a full latching shutdown, e.g.
Rhold ensures that the SCR stays on when fired. The bias
The NCP101X welcomes two dissipating terms, the DSS
CC
ramp up (8.5 V) and down (7.5 V) when the SCR
DSS
Figure 25. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient
+ P
Figure 24. Two Bipolars Ensure a Total Latch−Off of the SMPS in Presence of an OVP
MOSFET
OVP
. When the PDIP−7 package is
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
10 k
10 k
BAT54
qJA
Rhold
12 k
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down
16
voltage, the NPN biases the PNP and fires the equivalent
SCR, permanently bringing down the FB pin. The
switching pulses are disabled until the user unplugs the
power supply.
maximum power the device can thus evacuate is:
1.0 W for an ambient of 50 C. The losses inherent to the
MOSFET R
formula:
is the worse case peak current (at the lowest line input), d is
the converter operating duty−cycle and R
MOSFET resistance for T
valid for Discontinuous Conduction Mode (DCM)
operation where the turn−on losses are null (the primary
current is zero when you restart the MOSFET). Figure 25
gives a possible layout to help drop the thermal resistance.
When measured on a 35 mm (1 oz) copper thickness PCB,
we obtained a thermal resistance of 75 C/W.
Pmax +
+
CV
cc
1
2
3
4
T Jmax * Tambmax
Pmos + 1
DSon
R qJA
can be evaluated using the following
3
· Ip 2 · d · R DSon
8
7
5
J
= 100 C. This formula is only
Drain
(eq. 12)
which gives around
(eq. 13)
DSon
, where Ip
, the