MC74HC541ADWG ON Semiconductor, MC74HC541ADWG Datasheet
MC74HC541ADWG
Specifications of MC74HC541ADWG
MC74HC541ADWGOS
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MC74HC541ADWG Summary of contents
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... Chip Complexity: 134 FETs or 33.5 Equivalent Gates • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 March, 2009 − Rev. 6 http://onsemi ...
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... A5 Figure 1. Pinout: 20−Lead Packages (Top View) Data Inputs Output Enables ORDERING INFORMATION Device MC74HC541AN MC74HC541ANG MC74HC541ADW MC74HC541ADWG MC74HC541ADWR2 MC74HC541ADWR2G MC74HC541ADT MC74HC541ADTG MC74HC541ADTR2 MC74HC541ADTR2G MC74HC541AF MC74HC541AFG MC74HC541AFEL MC74HC541AFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb− ...
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... Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. 6. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...
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... Maximum Input Capacitance IN C Maximum 3−State Output Capacitance (High Impedance State Output) OUT 9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). C Power Dissipation Capacitance (Per Buffer) (Note 10) PD 10. Used to determine the no− ...
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INPUT A 50% 10% t PLH 90% 50% OUTPUT Y 10% t TLH Figure 3. Switching Waveform OE1 or OE2 50 PZL PLZ OUTPUT Y 50% t PZH OUTPUT Y 50% Figure 4. Switching Waveform ...
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INPUTS A1, A2, A3, A4, A5, A6, A7, A8 (PINS Data input pins. Data on these pins appear in non−inverted form on the corresponding Y outputs, when the outputs are enabled. CONTROLS ...
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SEATING PLANE 20X 0. 18X PACKAGE DIMENSIONS PDIP−20 N SUFFIX PLASTIC DIP PACKAGE CASE 738−03 ISSUE ...
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K 20X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT 1 0.15 (0.006 −V− 0.100 (0.004) −T− SEATING PLANE 16X 0.36 PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX ...
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... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...