MB15F03SL Fujitsu Media Devices, MB15F03SL Datasheet - Page 3

• Manufacturer Part Number: MB15F03SL
• Description: Dual Serial Input PLL Frequency Synthesizer
• Manufacturer: Fujitsu Media Devices

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SSOP
PIN DESCRIPTION
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Pin no.
BCC
16
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
LD/fout
GND
OSC
GND
name
Xfin
Clock
V
V
Do
PS
Data
PS
Do
fin
Pin
fin
LE
CCRF
CCIF
RF
IF
RF
RF
IF
IF
RF
RF
IN
IF
I/O
O
O
O
–
–
–
–
I
I
I
I
I
I
I
I
I
Ground for RF-PLL section.
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
Ground for the IF-PLL section.
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
Power supply voltage input pin for the IF-PLL section.
Lock detect signal output (LD)/phase comparator monitoring
output (fout).
The output signal is selected by LDS bit in the serial data.
LDS bit = “H” ; outputs fout signal
LDS bit = “L” ; outputs LD signal
Power saving mode control for the IF-PLL section. This pin must be set at
“L” during Power-ON. (Open is prohibited.)
PS
PS
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
Power saving mode control for the RF-PLL section. This pin must be set at
“L” during Power-ON. (Open is prohibited.)
PS
PS
Prescaler complementary input for the RE-PLL section.
This pin should be grounded via a capacitor.
Power supply voltage input pin for the RF-PLL section, the shift register
and the oscillator input buffer. When power is OFF, latched data of RF-PLL
is lost.
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
Load enable signal inpunt (with a schmitt trigger input buffer.)
When the LE bit is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
Serial data input (with a schmitt trigger input buffer.)
A data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit in
the serial data.
Clock input for the 23-bit shift register (with a schmitt trigger input buffer.)
One bit of data is shifted into the shift register on a rising edge of the clock.
IF
IF
RF
RF
= “H” ; Normal mode
= “L” ; Power saving mode
= “H” ; Normal mode
= “L” ; Power saving mode
Descriptions
MB15F03SL
3