MB86292 Fujitsu Media Devices Limited, MB86292 Datasheet
MB86292
Related parts for MB86292
MB86292 Summary of contents
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... The MB86292 is a graphics display controller with an on-chip geometry processor and digital video capture facility. It can be connected to FCRAM. Connecting the MB86292 to FCRAM which has lower latency upon a paging error speeds up the random access to memory, resulting in faster display and drawing. In addition, integrating the geometry processor reduces the CPU load, thereby improving the performance of the entire system ...
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... MB86292 (Continued) • Drawing features : Drawing at a peak rate of 800 Mpixel/s (at an internal operating frequency of 100 MHz) 2D drawing functions : Point, line, triangle, polygon, BLT and pattern drawing 3D drawing functions : Point, line, triangle drawing and hidden surface removal by Z-buffering Special effects : Anti-aliasing, bold/dashed-line processing, alpha blending, Gouraud shading, texture map- ping (bilinear filtering, perspective correct) , and tiling • ...
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... Input the high level. TESTH Notes : The PLLVDD should be separated on the board. Insert a bypass capacitor with a superior high-frequency characteristic between the power supply and ground. Place the capacitor as near the pins as possible. (TOP VIEW) MB86292 www.DataSheet4U.com 192 TESTH 191 GV 190 VSYNC ...
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... INT MODE0-MODE2 TESTL, TESTH CLK S CKM Clock CLKSEL0- CLKSEL1 OSCOUT OSCCNT 4 DCLKO DCLKI HSYNC VSYNC CSYNC DISPE GV R3-R7 G3-G7 MB86292 B3-B7 Graphics Controller RGBEN HQFP256 CCLK VI0-VI7 MD0-MD63 MA0-MA13 MRAS MCAS MWE MDQM0-MDQM7 MCLKO MCLKI www.DataSheet4U.com Video output interface Vide capture interface Graphics memory ...
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... Input Test signal Note : The host interface can connect the MB86292 to the SH4 (SH7750) or SH3 (SH7709) from Hitachi Ltd. the V832 from NEC the SPARClite (MB86833) from Fujitsu without any external circuit in between. (Using the SRAM interface allows the MB86292 to use another CPU.) The host CPU is set by the MODE0 and MODE1 pins as shown below ...
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... MB86292 Notes : The host interface transfers data signals at a fixed width of 32 bits. There are 23 lines for address signals handled in double words (32 bits) and 32 Mbytes of address space. The external bus can be used at an operating frequency of 100 MHz maximum. The RDY signal at the low level sets the ready state in the SH4 or V832 mode; the signal at the low level sets the wait state in the SH3 mode ...
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... Output MCLKI Input Notes : The graphics memory interface connects the MB86292 to the external memory used for graphical image data. The interface can directly accept 128-Mbit SDRAM or 64-Mbit SDRAM (with a 16-bit or 32-bit data bus) without any external circuit. Memory bus data can be selected between 64 bits and 32 bits. To use 32-bit data, leave the MD32-MD63 ...
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... MB86292 CKM L Select internal PLL output. H Select host CPU bus clock (BCLKI). • Use the CLKSEL pin to select the input clock frequency for using the internal PLL with CKM CLKSEL1 CLKSEL0 L L Input 13.5 MHz Input 14.32 MHz Input 17.73 MHz Reserved Note : Immediately after turning the power supply on, input a pulse whose low level period is 500 ns or more to the S pin before setting it to high level ...
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... BLOCK DIAGRAM D0-D31 External Host Bus of Interface Host CPU A2-A24 MD0-MD63 External SDRAM Memory or Controller FCRAM MA0-MA13 MB86292 www.DataSheet4U.com RBT656 Capture Controller Display Controller DRGB 2D/3D Geometry Rendering Engine Engine 9 ...
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... FUNCTION BLOCKS Host Interface This block allows the MB86292 to be connected to the SH3 or SH4 microprocessor from Hitachi Ltd., the V83x microprocessor from NEC the SPARCLite from Fujitsu without any external circuit in between. The block provides an interface to transfer display list and texture pattern data directly from main memory to this device’s graphics memory or internal register using the external DMA controller ...
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... Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Rating Symbol Min V * 0.5 DDL V 0.5 DDH V 0 POW Tstg 55 Value Symbol Min Typ V * 2.3 2.5 DDL V 3.0 3.3 DDH MB86292 www.DataSheet4U.com Unit Max 3.0 V 4.0 0.5 ( 4.0) V DDH 125 C Unit Max 2.7 V 3.6 V 0.3 V DDH 0 ...
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... MB86292 ELECTRICAL CHARACTERISTICS 1. DC Characteristics Paramater Output voltage (“H” level Output voltage (“L” level) * Output current (“H” level) Output current (“L” level) Input leakage current Pin capacitance *1 : Value when 100 A current flows into output pins Value when 100 A current flows into output pins. ...
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... Output Output Output 3 Output measurement standard : tpLZ : pHL t pZL 0 tpHZ : V 0 Else : MB86292 www.DataSheet4U.com ( 80% 20 pLH t pZH pLZ 0 pHZ 0 ...
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... MB86292 (1) Host Interface Clock Parameter BCLKI frequency BCLKI H period BCLKI L period Host interface signals Parameter Address setup time Address hold time BS setup time BS hold time CS setup time CS hold time RD setup time RD hold time WE setup time WE hold time Write data setup time ...
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... D0~D31, DTACK, DRACK Read/write enable (RD, WE) setup and hold times BCLKI BS CS RD, WE, A24 (MWR) 1/f BCLKI t LBCLKI ADS BSS CSS ADH BSH WDS DAKS DRKS WDH DAKH RDS WES MB86292 www.DataSheet4U.com , CSH , t DRKH t RDH, t WEH 15 ...
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... MB86292 DREQ/INT output delay time BCLKI DREQ (output) INT (output) RDY delay value (with respect to CS) BCLKI CS RDY (output DRQD INTD High-Z t RDYDZ www.DataSheet4U.com High-Z t RDYDZ ...
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... RDY, D output delay values (The D pin outputs effective data from the RDY assert cycle.) BCLKI RD (CS) t RDDZ D0~D31 High-Z (output) RDY MODE signal hold time RESET MODE0~ MODE2 t RDD output data t t RDYD RDYD t MODH MB86292 www.DataSheet4U.com t RDDZ High-Z 17 ...
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... MB86292 (2) Video Interface Clock Parameter CLK frequency CLK H period CLK L period DCLKI frequency DCLKI H period DCLKI L period DCLKO frequency Input signals Parameter HSYNC input pulse width HSYNC input setup time HSYNC input hold time VSYNC input pulse width *1 : Applied only in PLL synchronization mode (CKS ...
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... HSYNC signal setup and hold t HDCLKI DCLKI HSYNC (input) Output signal delay DCLKO R7-R3, G7-G3, B7-B3, MD63-MD55*, HSYNC (output), VSYNC (output), CSYNC Valid if RGBEN 0 1/f CLK t LCLK 1/f DCLKI t LDCLKI t t SHSYNC HHSYNC RGB DEO DHSYNC DVSYNC DCSYNC DGV MB86292 www.DataSheet4U.com , 19 ...
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... MB86292 (3) Graphics Memory Interface Clock Parameter MCLKO frequency MCLKO H period MCLKO L period MCLKI frequency MCLKI H period MCLKI L period MCLKI delay to MCLKO * : In BUS asynchronous mode, the frequency is half the internal PLL oscillation frequency. In Bus synchronous mode, the frequency is the same as BCLKI. Input/output signals ...
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... Input signal setup and hold times MCLKO MD0~MD63 MCLKI signal delay MCLKO MCLKI Output signal delay MCLKO MA0~MA13, MRAS, MCAS, MWE, MD0~MD63, MDQM0~MDQM7 1/f , 1/f MCLKO MCLKI , HMCLKI LMCLKO LMCLKI Input data t t MDIDS MDIDH t OID MADS MDODS MDQMDS MADH MB86292 www.DataSheet4U.com , MDODH MDQMDH 21 ...
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... MB86292 (4) PLL Standards Parameter Min Input frequency Output frequency Duty ratio 101.3 Jitter 180 ps 22 Value Typ Max 14.31818 MHz 200.45452 MHz Multiplied by 14 PLL output clock H/L pulse width 93.1 ratio Cycle difference between two 150 ps consecutive cycles www.DataSheet4U.com Remarks ...
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... ORDERING INFORMATION Part Number MB86292PFFS-G-BND Package 256-pin plastic QFP (FPT-256P-M09) MB86292 www.DataSheet4U.com Remarks 23 ...
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... MB86292 PACKAGE DIMENSION 256-pin plastic QFP (FPT-256P-M09) 30.60±0.20(1.205±.008)SQ 28.00±0.10(1.102±.004)SQ 156 157 INDEX 208 LEAD No. 1 0.40(.016) 2000 FUJITSU LIMITED F256025S-c-2 *Pins width and pins thickness include plating thickness. 0.145±0.055 (.006±.002) ...
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... MB86292 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U ...