CDS-1402 Datel, Inc., CDS-1402 Datasheet - Page 3

• Manufacturer Part Number: CDS-1402
• Description: Faster-settling Correlated Double Sampling Circuit: 14-bit
• Manufacturer: Datel, Inc.

TECHNICAL NOTES
1. To achieve specified performance, all power supply pins
2. In the CDS configuration, to avoid saturation of the S/H
3. The combined video and reference/offset signal from the
4. To use as a CDS circuit, tie pin 8 (S/H2 SUMMING NODE)
5. To use as a dual S/H, leave pin 7 (S/H1 ROUT) and pin 8
6. See Figure 4 for acquisition time versus accuracy and input
GENERAL DESCRIPTION
at the output of the CDS-1402 every 200ns. This correlates
with the fact that an acquisition time of 100ns is required for
each internal S/H amplifier (5V step acquired to ±0.01%
accuracy). The input and output of the CDS-1402 can swing
up to ±2.5 Volts.
The functionally complete CDS-1402 is packaged in a single,
24-pin, ceramic DDIP. It operates from ±5V analog and +5V
digital supplies and typically consumes 350mW. Though the
CDS-1402's approach to CDS appears straightforward (see
Funtional Description ), the circuit actually exploits an elegant
architecture whose tradeoffs enable it to offer wide-bandwidth,
low-noise and high-throughput combinations unachievable until
now. The CDS-1402, a generic type of circuit, can be used
with most 10 to 14-bit A/D converters. However, DATEL offers
A/D converters optimized for use with CDS-1402.
POWER REQUIREMENTS
Power Supply Ranges
Power Supply Currents
Power Dissipation
Power Supply Rejection
should be bypassed with 2.2µF tantalum capacitors in
parallel with 0.1µF ceramic capacitors. All ANALOG
GROUND (pins 5, 14, 21 and 23) and DIGITAL GROUND
(pin 15) pins should be tied to a large analog ground plane
beneath the package.
amplifiers, the maximum analog inputs and conditions are
as follows:
CCD array must be applied to S/H2, while the reference/
offset signal is applied to S/H1.
to either pin 6 (S/H1 OUT), through a 100 Ohm
potentiometer, or directly to pin 7 (S/H1 ROUT). In both
cases, the CCD's output is tied to pins 3 (ANALOG INPUT
1) and 4 (ANALOG INPUT 2). As shown in Figure 5, the
100
(S/H2 SUMMING NODE) floating. Pin 6 (S/H1 OUT) will
be the output of S/H1 and pin 22 (V OUT) will be the output
of S/H2.
voltage step amplitude.
®
+5V Analog Supply
–5V Analog Supply
+5V Digital Supply
+5V Analog Supply
–5V Analog Supply
+5V Digital Supply
(ANALOG INPUT 1 – ANALOG INPUT 2) < ±3.2V
ANALOG INPUT 1 < ±3.2V
potentiometer is for gain matching.
®
(continued)
MIN.
–4.75
+4.75
+4.75
—
—
—
—
—
+25°C
TYP.
+5.0
–5.0
+5.0
+35
–35
350
+2
60
MAX.
+5.25
–5.25
+5.25
+50
–50
500
+5
—
3
MIN.
+4.75
–4.75
+4.75
—
—
—
—
—
FUNCTIONAL DESCRIPTION
Correlated Double Sampling
All photodetector elements (photodiodes, photomultiplier tubes,
focal plane arrays, charge coupled devices, etc.) have unique
output characteristics that call for specific analog-signal-
processing (ASP) functions at their outputs. Charge coupled
devices (CCD’s), in particular, display a number of unique
characteristics. Among them is the fact that the "offset error"
associated with each individual pixel (i.e., the apparent
photonic content of that pixel after having had no light incident
upon it) changes each and every time that particular pixel is
accessed.
Most of us think of an offset as a constant parameter that
either can be compensated for (by performing an offset
adjustment) or can be measured, recorded, and subtracted
from subsequent readings to yield more accurate data.
Contending with an offset that varies from reading to reading
requires measuring and recording (or capturing and storing)
the offset each and every time, so it can be subtracted from
each subsequent data reading.
The "double sampling" aspect of CDS refers to the operation of
sampling and storing/recording a given pixel’s offset and then
sampling the same pixel’s output an instant later (with both the
offset and the video signal present) and subsequently
subtracting the two values to yield what is referred to as the
"valid video" output for that pixel.
The "correlated" in CDS refers to the fact that the two samples
must be taken close together in time because the offset is
constantly varying. Reasons for this phenomena are
discussed below.
At the output of all CCD's, transported pixel charge (electrons)
is converted to a voltage by depositing the charge onto a
capacitor (usually called the output or "floating" capacitor).
The voltage that develops across this capacitor is obviously
proportional to the amount of deposited charge (i.e., the
number of electrons) according to V = Q/C. Once settled,
the resulting capacitor voltage is buffered and brought to the
CCD’s output pin as a signal whose amplitude is proportional
to the total number of photons incident upon the relevant pixel.
After the output signal has been recorded, the floating
capacitor is discharged ("reset", "clamped", "dumped") and
made ready to accept charge from the next pixel. This is when
the problems begin. (This is a somewhat oversimplified
explanation in that the floating capacitor is not usually
"discharged" but, in fact, "recharged" to some predetermined
dc voltage, usually called the "reference level". The pixel offset
appears as an output deviation from that reference level.)
0 to +70°C
TYP.
+5.0
–5.0
+5.0
+35
–35
350
+2
60
MAX.
+5.25
–5.25
+5.25
+50
–50
500
+5
—
MIN.
+4.75
–4.75
+4.75
—
—
—
—
—
–55 to +125°C
TYP.
+5.0
–5.0
+5.0
+35
–35
350
+2
60
CDS-1402
MAX.
+5.25
–5.25
+5.25
+50
–50
500
+5
—
UNITS
Volts
Volts
Volts
mW
mA
mA
mA
dB