HD49335F Renesas Electronics Corporation., HD49335F Datasheet
HD49335F
Related parts for HD49335F
HD49335F Summary of contents
Page 1
... CDS/PGA & 10-bit A/D TG Converter Description The HD49335F/ CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip. There are address map and timing generator charts besides this specification. May be contacted to our sales department if examining the details ...
Page 2
... HD49335F/HF Pin Arrangement BLKC 50 CDS_in BLKFB 53 BLKSH Test2 56 Test1 57 DLL_C MON 60 41cont SDATA 63 SCK 64 Pin Description Pin No. Symbol Description 1 ID Odd/even number line detecting pulse output pin 2 DV 1,2 CDS Digital ground + ADC output buffer ground (0 V) ...
Page 3
... HD49335F/HF Pin Description (cont.) Pin No. Symbol Description 30 XV1 V.CCD transfer pulse output-1 31 XV2 V.CCD transfer pulse output-2 32 XV3 V.CCD transfer pulse output-3 33 XV4 V.CCD transfer pulse output-4 34 CH1 Read out pulse output-1 35 CH2 Read out pulse output-2 36 CH3 Read out pulse output-3 ...
Page 4
... HD49335F/HF Input/Output Equivalent Circuit Pin Name Digital output D0 to D9, HD_in, VD_in, H1A, H2A, 1/2clk_o, 1/4clk_o, 41cont, SUB_SW, SUB_PD ID, RG, MON, XV1 to XV4, CH1 to CH4, XSUB Digital input CLK_in, HD_in, VD_in, ADCLK, OBP, SPBLK, SPSIG, CS, SCK, SDATA, PBLK, OEB, Reset, Test1, Test2, SUB_SW, STROB ...
Page 5
... HD49335F/HF Block Diagram SUB_SW SUB_PD STROB ADC_in CDS_in CDS BLKSH BLKC DC offset compensation BLKFB circuit Rev.1.0, Feb.25.2004, page Timing generator DLL 10bit PGA ADC Serial Bias interface generator Reset ...
Page 6
... HD49335F/HF Internal Functions Functional Description • CDS input CCD low-frequency noise is suppressed by CDS (correlated double sampling). The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. * Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2. 31.40 dB. * • ...
Page 7
... HD49335F/HF 3. Automatic Offset Calibration Function and Black-Level Clamp Data Settings The DAC DC voltage added to the output of the PGA amplifier is adjusted by automatic offset calibration. The data, which cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data (14 LSB to 76 LSB) set by register are added and input to the DAC ...
Page 8
... HD49335F/HF 6. ADC Digital Output Control Function The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5 show the output functions and the codes. Table 3 ADC Digital Output Functions Hi Same as in table 4. ...
Page 9
... HD49335F/HF 7. Adjustment of Black-Level S/H Response Frequency Characteristics The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the register settings, as shown in table 6. Table 6 SHSW CR Time Constant Setting [0] [1] [2] [ Time Constant (Typ) 2.20 nsec (cutoff frequency conversion) (72 MHz) ...
Page 10
... HD49335F/HF Timing Chart Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used When CDS_in input mode is used N CDS_in SP1 SP2 ADCLK When ADC_in input mode is used N+1 N ADC_in ADCLK Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used • ...
Page 11
... HD49335F/HF Detailed Timing Specifications Detailed Timing Specifications when CDSIN Input Mode is Used Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing specification. CDS_in SP1 SP2 ADCLK Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used ...
Page 12
... HD49335F/HF Detailed Timing Specifications at Pre-Blanking Figure 5 shows the pre-blanking detailed timing specifications. PBLK Digital output ADC (D0 to D9) data Figure 5 Detailed Timing Specifications at Pre-Blanking Detailed Timing Specifications when ADCIN Input Mode is Used Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification. ...
Page 13
... HD49335F/HF Dummy Clamp It adjusts the mis-clamp which occurs when taking the photo under the highlight conditions. (Like a sun) Normally it woks with the OB clamp, however when black level is out of the range caused by hightlight enter to OB part, it changes to clamp processing by dummy bit level. Resister settings are follows. ...
Page 14
... V +0.3 V +0.3 V °C mW ° 3 3.0 V, and kΩ) DD BIAS Unit Test Conditions Remarks V 2 MHz LoPwr = low * HD49335HF 2 MHz LoPwr = high * HD49335F V CS, SCK, SDATA – µ 3 µ bit LSBp MHz CLK LSB ...
Page 15
... HD49335F/HF Electrical Characteristics (cont.) (Unless othewide specified 25°C, AV • Items for CDSIN Input Mode Item Symbol Consumption current (1) I DD1 Consumption current (2) I DD2 CCD offset tolerance range V CCD Timing specifications (1) t CDS1 Timing specifications (2) t CDS2 Timing specifications (3) t CDS3 ...
Page 16
... HD49335F/HF Electrical Characteristics (cont.) (Unless othewide specified 25°C, AV • Items for ADCIN Input Mode Item Symbol Consumption current (3) I DD3 Consumption current (4) I DD4 Timing specifications (14) t ADC1 Timing specifications (15) t ADC2 Timing specifications (16) t ADC3 Timing specifications (17) t AHLD4 ...
Page 17
... HD49335F/HF Serial Interface Specifications Timing Specifications t INT1 Latches SDATA at SCK rising edge CS SCK SDATA D8 D9 D10 D11 D12 STD2(Upper data) Figure 8 Serial Interface Timing Specifications Item Min Max f — 5 MHz SCK — INT1 — — ...
Page 18
... HD49335F/HF Explanation of Serial Data of CDS Part Serial data of CDS part are assigned to address H’F0 to H’F8. Functions are follows. Address • PGA gain ( address H’F0) Details are referred to page 5 block diagram. At CDS_in mode: –2. 0.132 dB × N (Log linear) At ADC_in mode: 0.57 times + 0.01784 times × ...
Page 19
... HD49335F/HF • Output mode ( address H’F1 and address H’ test mode. Combination details are table Normally set to all 0. • SHA-fsel ( address H’F1 LPF switching of SH amplifier. Frequency characteristics are referred to page 8. To get rough idea, set the double cut off frequency point with using. • ...
Page 20
... HD49335F/HF Address • MON ( address H’F4) Select the pulse which output to pin MON (pin 60). When D0 to D2: 0, Fix to Low When 2, SP1 When 4, OBP When 6, CPDM • H12Baff ( address H’F4) Select the buffer size which output to pin H1A, H2A (pin 22, 26). ...
Page 21
... HD49335F/HF Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss quantization) occurs to the image. Differential code and gray code are recommended for this countermeasure. ...
Page 22
... HD49335F/HF • Address H’F5 sets the DLL delay time and selects the 1/4 phase. Details are on the next page. And D15 of address H’F8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid. Divided mode address H’ D14 of address H’F8 • ...
Page 23
... HD49335F/HF (3) Setting method of DLL 1. DLL step decides the how many divide the 1 cycle of sensor CLK. For reference, set 1 ns(when 2 ns DLL_current bit = 0, when 1 set to 1 ns) Can be set steps by 4 steps. Steps = N); possible to set Recommended steps is clk_in = when MHz: H'0E(60 steps) ...
Page 24
... HD49335F/HF Operation Sequence at Power CLK_in Hardware Reset HD49335 serial data transfer SP1 SP2 Start control ADCLK of TG and OBP camera DSP etc. RESET bit Automatic offset calibration The following describes the above serial data transfer. For details of resistor settings are referred to serial data function table ...
Page 25
... HD49335F/HF Timing Specifications of High Speed Pulse H1, H2, RG waveform tr H2 90% 10 twh 90% 10% RG twh Item min typ H1/ XV1 to 4 — — CH1 to 4 — — XSUB/SUB_SW — — two Item min typ H1/H2 overlap 12 20 Rev.1.0, Feb.25.2004, page ...
Page 26
... HD49335F/HF Notice for Use 1. Careful handling is necessary to prevent damage due to static electricity. 2. This product has been developed for consumer applications, and should not be used in non-consumer applications this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to prevent latchup, a ceramic capacitor of 0.1 µ ...
Page 27
... HD49335F/HF Example of Recommended External Circuit Slave mode Pin 57(Test1 = Low) 47 3.0V + 47/6 0.1 47 XV3 33 XV4 to V.Baff CH1 34 CH2 35 CH3 36 CH4 37 XSUB 38 SUB_SW/ADCK_in 39 to CCD 40 SUB_PD STROB/Vgate ADC_in 44 BIAS 33k 45 0.1 46 VRB 0.1 47 VRT VRM 0 0.1 47/6 CCD signal input Master mode Pin 57(Test1 = Hi ...
Page 28
... HD49335F/HF CDS single operating mode Pin 56(Test2 = Low) Pin 57 is "Don't care" in this mode. 47 3.0V + 47/6 0 ADC_in 44 33k 45 0.1 46 0 0.1 CCD signal input Serial data when CDS single operation mode are following resister specifications. (Latch timing specification is same as normal mode) ...
Page 29
... HD49335F/HF Package Dimensions 12.0 ± 0.2 10 *0.21 ± 0.05 0.19 ± 0.04 1.25 *Dimension including the plating thickness Base material dimension Rev.1.0, Feb.25.2004, page 0.08 M 1.0 1.25 0.10 0.50 ± 0.1 Package Code JEDEC JEITA Mass (reference value January, 2003 Unit: mm 0˚ – 8˚ TFP-64C — ...
Page 30
Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...