HD49335F Renesas Electronics Corporation., HD49335F Datasheet - Page 10

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HD49335F

Manufacturer Part Number
HD49335F
Description
Cds/pga And 10-bit A/d Tg Converter
Manufacturer
Renesas Electronics Corporation.
Datasheet
HD49335F/HF
Timing Chart
Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
• The ADC output (D0 to D9) is output at the rising edge of the ADCLK in both modes.
• Pipe-line delay is ten clock cycles when CDSIN is used and nine when ADCIN is used.
• In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.
Rev.1.0, Feb.25.2004, page 10 of 29
CDS_in
SP1
SP2
ADCLK
D0 to D9
ADC_in
ADCLK
D0 to D9
When CDS_in input mode is used
When ADC_in input mode is used
Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used
N
0
N 10
N 9
N
N+1
1
N+1
N 9
N 8
N+2
2
N+2
N 8
N+8
~
N 1
N+9
9
N+9
N 1
N
N+10
10
N+10
N+1
N
N+11
11
N+11

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