USBN9604 National Semiconductor, USBN9604 Datasheet
USBN9604
Manufacturer Part Number
USBN9604
Description
USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support
Manufacturer
National Semiconductor
Datasheet
1.USBN9604.pdf
(60 pages)
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© National Semiconductor Corporation, 2003
USBN9603/USBN9604 Universal Serial Bus
Full Speed Node Controller with Enhanced DMA Support
General Description
The USBN9603/4 are integrated, USB Node controllers.
Other than the reset mechanism for the clock generation cir-
cuit, these two devices are identical. All references to “the
device” in this document refer to both devices, unless other-
wise noted.
The device provides enhanced DMA support with many au-
tomatic data handling features. It is compatible with USB
specification versions 1.0 and 1.1, and is an advanced ver-
sion of the USBN9602.
The device integrates the required USB transceiver with a
3.3V regulator, a Serial Interface Engine (SIE), USB end-
point (EP) FIFOs, a versatile 8-bit parallel interface, a clock
generator and a MICROWIRE/PLUS™ interface. Seven
endpoint pipes are supported: one for the mandatory con-
trol endpoint and six to support interrupt, bulk and isochro-
nous endpoints. Each endpoint pipe has a dedicated FIFO,
8 bytes for the control endpoint and 64 bytes for the other
endpoints. The 8-bit parallel interface supports multiplexed
and non-multiplexed style CPU address/data buses. A pro-
grammable interrupt output scheme allows device configu-
ration for different interrupt signaling requirements.
Block Diagram
National Semiconductor is a registered trademark of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
- May 1998
Serial Interface Engine (SIE)
CS
Transceiver
Media Access Controller (MAC)
Physical Layer Interface (PHY)
D+
RD
Microcontroller Interface
Endpoint/Control FIFOs
D-
WR
Upstream Port
A0/ALE D7-0/AD7-0
Outstanding Features
VReg
Low EMI, low standby current, 24 MHz oscillator
Advanced DMA mechanism
Fully static HALT mode with asynchronous wake-up
for bus powered operation
5V or 3.3V operation
Improved input range 3.3V signal voltage regulator
All unidirectional FIFOs are 64 bytes
Power-up reset and startup delay counter simplify sys-
tem design
Simple programming model controlled by external controller
Available in two packages
— USBN9603/4SLB: small footprint for new designs
— USBN9603/4-28M: standard package, pin-to-pin
and portable applications
compatible with USBN9602-28M
USB Event
INTR
Recovery
Detect
Clock
Generator
Oscillator
24 MHz
Clock
MODE1-0
RESET
V
GND
XIN
XOUT
CLKOUT
V3.3
AGND
CC
Revision 1.3
www.national.com
June 2003
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