CS1301 National Semiconductor, CS1301 Datasheet

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CS1301

Manufacturer Part Number
CS1301
Description
National Semiconductor [Media Coprocessor]
Manufacturer
National Semiconductor
Datasheet
© 2002 National Semiconductor Corporation
Geode™ CS1301/CS1311 Multimedia Companion:
Media Coprocessor
General Description
The National Semiconductor
CS1311 multimedia companions act as coprocessors to
decode multimedia in National’s Geode single chip proces-
sor-based systems (i.e., SC1200/SC1201, SC2200, and
SC3200, hereafter referred to as SCx200). They provide a
multimedia experience for an Information Appliance (IA)
user that cannot typically be achieved on a PC.
By implementing a dedicated coprocessor to perform multi-
media tasks, a high quality video viewing experience can
be achieved. This high quality is achieved by having a
coprocessor architecture that is ideally suited for decoding
digital media. In addition, since the decoding is not occur-
ring on the SCx200, system events cannot interrupt the
Internal Block Diagram
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YUV 4:2:2 up to 81 MHz
CCIR-656 Digital Video
Huffman Decoder
up to 22 MHz AI_SCK
8/16-bit data I
Slice-At-A-Time
Stereo Digital Audio
MPEG-1 & 2
(40 Mpix/sec)
2
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®
Geode™ CS1301 and
Coprocessor
VLIW
CPU
Audio In
Video In
Timers
VLD
16K D$
32K I$
Main Memory Interface
PCI Interface
SDRAM
1
coprocessor’s task of decoding media and thereby causing
stuttering of sound or interruptions in the video.
Lower power consumption can also be achieved using the
SCx200/CS1301
CS1301/CS1311 has an architecture specifically designed
for decoding media. The architecture is such that while
decoding media, power is not consumed by portions of the
system that are not used to decode media. Since the
SCx200 is not decoding the media locally, it is able to go
into a lower power state. When the CS1301/CS1311 is not
decoding media, it uses almost no power.
Additionally, since the architecture is designed for decoding
media, fewer CS1301/CS1311 cycles are required.
ACCESS.bus
Coprocessor
S/PDIF Out
Video Out
Audio Out
Interface
Image
or
32-Bit Data
(up to 664 MB/sec)
SCx200/CS1311
16/32-Bit Data I
2/4/6/8 Ch. Digital Audio
External Bus
PCI V2.1 (32 bits, 33 MHz)
up to 22 MHz AO_SCK
IEC958 up to 40 Mbit/sec
ACCESS.bus Interface
to EEPROM
CCIR-656 Digital Video
Down and Up Scaling
YUV --> RGB
(50 Mpix/sec)
Preliminary
solution.
www.national.com
August 2002
Revision 2.2
2
S DC,
The

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CS1301 Summary of contents

Page 1

... Since the SCx200 is not decoding the media locally able to go into a lower power state. When the CS1301/CS1311 is not decoding media, it uses almost no power. Additionally, since the architecture is designed for decoding media, fewer CS1301/CS1311 cycles are required ...

Page 2

... Features General Features Physical Process 0.25-micron CMOS Packaged in a 292-terminal TEPBGA (Thermally Enhanced Plastic Ball Grid Array) Power supply: — CS1301: 2.5V Core; 3.3V I/O (5V tolerant) — CS1311: 2.2V Core; 3.3V I/O (5V tolerant) Consumption 1300 mA; 3.5W Power-down 300 mA Case Temperature 0° to 85°C Central Processing Unit Clock speed: — ...

Page 3

... CS1311 EEPROM Revision 2.2 1.1 IMPORTANT DESIGN NOTE The CS1301/CS1311 was designed general pur- pose media data processor. As such, the CS1301/CS1311 is capable of far more than the current National CS1301/CS1311 solution. The solution that National is pro- viding is only one possible implementation of the CS1301/CS1311 and only this implementation is fully sup- ported by National Semiconductor. In order to maintain software compatibility with National’ ...

Page 4

... Software Support National provides a reference schematic and the associ- ated software for a processor/coprocessor solution using the Geode SCx200 and the CS1301/CS1311. This imple- mentation is currently supplied as a multimedia decoder for CE player under Microsoft Windows CE.net or Linux. Future support for Microsoft Windows XP is planned. Since ...

Page 5

... System Architecture (Continued) 1.2.3 Software Architecture Overview Figure 1-2 demonstrates the interaction between the vari- ous software layers. File Source Geode™ SCx200 Geode™ CS1301/CS1311 TSSA* TRead Demux * TriMedia Streaming Software Architecture Revision 2.2 Note: The shaded boxes indicate components provided by Microsoft Corporation. ...

Page 6

... DirectShow Filter www.national.com 1.2.4.1 Codec Software The codec software includes video and audio decoders and operates on the CS1301/CS1311 (see Table 1-1). This software performs the task of decoding the encoded media content, which are the workhorses of the solution. 1.2.4.2 Host Filter Software The DirectShow filter is the core piece of software that inte- grates the CS1301/CS1311 media companion with Microsoft DirectShow (see Table 1-2) ...

Page 7

... Geode software components are included. These are stan- dard components to be used in a non-media enabled appli- cation to support the required functions of an Information Appliance. In some cases, these drivers have been opti- mized to work with the CS1301/CS1311 (see Table 1-5). Available as IP Owner(s) Source/Binary ...

Page 8

... In and Audio In are supported by third party software solutions, not by the National Semiconductor solution. www.national.com Table 2-1 shows the types of I/O circuits used by the CS1301/CS1311 series. Note that the # symbol in a signal name indicates that the active or asserted state occurs when the signal low voltage level. Otherwise, the signal is asserted when at a high voltage level ...

Page 9

... MDQ28 MDQ29 MDQ31 MDQ22 MDQ20 MDQ17 MMA9 MMA7 MMA4 MMCK0 MMA3 MMA1 MMA11 MMA13 MCS# MDQ14 MDQ12 MDQ10 MCE0 MDQ0 Note: Signal names have been abbreviated in this figure due to space constraints. = GND Connection = CS1301 2.5V Core Power Connection; CS1311 2.2V Core Power Connection = 3.3V I/O Power Connection Figure 2-2. 292-TEPBGA Ball Assignment Diagram Revision 2 ...

Page 10

Signal Definitions (Continued) Table 2-2. Ball Assignment Sorted by Ball Number Ball No. Signal Name Type A1 PCI_AD23 I/O A2 PCI_IDSEL I A3 PCI_AD24 I/O A4 PCI_AD27 I/O A5 PCI_AD28 I/O A6 PCI_AD31 I/O A7 PCI_INTD# I/OD A8 PCI_INTB# I/O/OD ...

Page 11

Signal Definitions (Continued) Table 2-2. Ball No. Signal Name Type L9 V GND SS L10 V GND SS L11 V GND SS L12 V GND SS L13 V GND SS L17 V PWR CC L18 V PWR CC L19 V ...

Page 12

Signal Definitions (Continued) Table 2-3. Ball Assignment Sorted Alphabetically by Signal Name Signal Name Ball No. Signal Name AI_OSCLK B15 MM_DQ11 AI_SCK A16 MM_DQ12 AI_SD C15 MM_DQ13 AI_WS B16 MM_DQ14 AO_OSCLK B14 MM_DQ15 AO_SCK A14 MM_DQ16 AO_SD1 B13 MM_DQ17 AO_SD2 ...

Page 13

... External General Purpose Clock Source for Timers . Maximum 40 I MHz. I CS1301/CS1311 RESET Input. This pin can be tied to the PCI_RST# signal in the PCI bus systems. Upon releasing RESET, CS1301/CS1311 initiates its boot protocol. PWR PCI Voltage Reference. Determines the mode of operation of the PCI pins ...

Page 14

... SDRAM Output Clock ( TRI_CLKIN frequency). Two identi- cal outputs are provided to reliably drive several small memory configu- rations without external glue. A series terminating resistor close to CS1301/CS1311 is required to reduce ringing. For driving a 50 trace, a resistor recommended. The use of higher impedance traces in the SDRAM signals is not recom- mended ...

Page 15

... ID Select. Used as chip select during configuration read/write cycles. I/O Device Select Sustained TRI-STATE. Indicates whether any device on the bus has been selected. O Request. Driven by the CS1301/CS1311 as a PCI bus master to request use of the PCI bus. I Grant. Indicates to the CS1301/CS1311 that access to the PCI bus has been granted. ...

Page 16

... If configured as an input (power-up default): A positive transition on this incoming video clock pin samples VI_DATA[09:00] if VI_DVALID is high. If VI_DVALID is low, VI_DATA[09:00] is ignored. Clock and data rates MHz are supported. The CS1301/CS1311 supports an addi- tional mode where VI_DATA[09:08] in message passing mode are not affected by the VI_DVALID signal. ...

Page 17

... If configured as an input: VO_CLK is received from external display clock master circuitry. If configured as an output: The CS1301/CS1311 emits a programmable clock frequency. The emitted frequency can be set between approxi- mately 4 and 81 MHz with a sub-Hertz resolution. The clock generated is frequency accurate and has low jitter properties due to a combination of an on-chip DDS (Direct Digital Synthesizer) and VCO/PLL ...

Page 18

... AI_SCK is an input. AI_SCK receives the serial bit clock from the external A/D subsystem. This clock is treated as fully asynchronous to the CS1301/CS1311 main clock. When the AI module is programmed as the serial-interface timing mas- ter, AI_SCK is an output. AI_SCK drives the serial clock for the external A/D subsystem ...

Page 19

... S/PDIF Data Out. Self-clocking serial data stream as per IEC958, with 1937 extensions. Note that the low impedance output buffer requires series terminator close to CS1301/CS1311 in order to match the board trace impedance. This series terminator must be part of the voltage divider needed to create the coaxial output through the AC isola- tion transformer ...

Page 20

Signal Definitions (Continued) 2.2.9 ACCESS.bus Interface Signals Ball Signal Name No. IIC_SDA R19 IIC_SCL R20 2.2.10 JTAG Interface Signals Ball Signal Name No. JTAG_TDI F20 JTAG_TDO F18 JTAG_TCK F19 JTAG_TMS E20 2.2.11 Test and Measurement Interface Signals Ball Signal Name ...

Page 21

... PLL Subsystem. Should be AC bypassed otherwise left DC floating connected on-chip to V coil or other connection to board ground is needed; such a connection would create a ground loop. 2.5V CS1301 Core Power Connection (Total of 24). PWR 2.2V CS1311 Core Power Connection (Total of 24). PWR 3.3V I/O Power Connection (Total of 24). ...

Page 22

Signal Definitions (Continued) 2.3 REFERENCE VOLTAGES Outputs always drive to a level determined by the 3.3V I/O voltage, with the exception of Open Drain mode outputs. VREF_PCI Determined Mode PCI_AD00 PCI_AD27 PCI_AD01 PCI_AD28 PCI_AD02 PCI_AD29 PCI_AD03 PCI_AD30 PCI_AD04 PCI_AD31 PCI_AD05 ...

Page 23

Package Specifications NOTES: UNLESS OTHERWISE SPECIFIED. 1) SOLDER BALL COMPOSITION: SN 63%, PB 37%. 2) DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM N. 3) THE MOLD SURFACE AREA MAY INCLUDE DIMPLE FOR A1 ...

Page 24

... A.3 PRODUCT BRIEF REVISION HISTORY This section is a report of the revision/creation process of the product brief for the Geode CS1301/CS1311. Any revisions (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table below. Note: This product brief must be used in conjunction with the Philips Semiconductor PNX1300 Series Media Processors Data Book for a complete understanding of the CS1301/CS1311 (posted on National’ ...

Page 25

... DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 1 ...

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