AD9802 Analog Devices, AD9802 Datasheet - Page 9

• Manufacturer Part Number: AD9802
• Description: CCD Signal Processor For Electronic Cameras
• Manufacturer: Analog Devices

The actual implementation of this loop is slightly more compli-
cated as shown in Figure 19. Because there are two separate
CDS blocks, two black level feedback loops are required and
two offset voltages are developed. Figure 19 also shows an addi-
tional PGA block in the feedback loop labeled “RPGA.” The
RPGA uses the same control inputs as the PGA, but has the
inverse gain. The RPGA functions to attenuate by the same
factor as the PGA amplifies, keeping the gain and bandwidth of
the loop constant.
There exists an unavoidable mismatch in the two offset voltages
used to correct both CDS blocks. This mismatch causes a slight
difference in the offset level for odd and even pixels, called
“pixel-to-pixel offset” (see Specifications). The pixel-to-pixel
offset is an output referred specification, because the black level
correction is done using the output of the PGA.
Input Bias Level Clamping
The buffered CCD output is connected to the AD9802 through
an external coupling capacitor. The dc bias point for this cou-
pling capacitor is established during the clamping (CLPDM =
LOW) period using the “dummy clamp” loop shown in Figure
20. When closed around the CDS, this loop establishes the
desired dc bias point on the coupling capacitor.
Input Blanking
In some applications, the AD9802’s input may be exposed to
large signals from the CCD. These signals can be very large,
relative to the AD9802’s input range, and could thus saturate
on-chip circuit blocks. Recovery time from such saturation
conditions could be substantial.
REV. 0
IN
CCD
CDS1
CDS2
CDS
CONTROL
RPGA1
RPGA2
Figure 19.
Figure 20.
PGA
CLAMP
CLPDM
INPUT
INT1
INT2
PGA
LEVEL CLP
BLACK
TO ADC
ADC
CLPOB
NEG REF
–9–
To avoid problems associated with processing these transients,
the AD9802 includes an input blanking function. When active
(PBLK = LOW) this function stops the CDS operation and
allows the user to disconnect the CDS inputs from the CCD
buffer.
If the input voltage exceeds the supply rail by more than 0.3 V,
then protection diodes will be turned on, increasing current flow
into the AD9802 (see Equivalent Input Circuits). Such voltage
levels should be externally clamped to prevent device damage or
reliability degradation.
10-Bit Analog-to-Digital Converter (ADC)
The ADC employs a multibit pipelined architecture that is
well suited for high throughput rates while being both area and
power efficient. The multistep pipeline presents a low input
capacitance resulting in lower on-chip drive requirements. A
fully differential implementation was used to overcome head-
room constraints of the single +3 V power supply.
Direct ADC Input
The analog processing circuitry may be bypassed in the
AD9802. When ADCMODE (Pin 41) is taken high, the
ADCIN pin provides a direct input to the SHA. This feature
allows digitization of signals that do not require CDS and
gain adjustment. The PGA output is disconnected from the
SHA when ADCMODE is taken high.
Differential Reference
The AD9802 includes a 0.5 V reference based on a differential,
continuous-time bandgap cell. Use of an external bypass capaci-
tor reduces the reference drive requirements, thus lowering the
power dissipation. The differential architecture was chosen for
its ability to reject supply and substrate noise. Recommended
decoupling shown in Figure 21.
Internal Timing
The AD9802’s on-chip timing circuitry generates all clocks
necessary for operation of the CDS and ADC blocks. The user
needs only to synchronize the SHP and SHD clocks with the
CCD waveform, as all other timing is handled internally. The
ADCCLK signal is used to strobe the output data, and can be
adjusted to accommodate desired timing.
REF
VRT
VRB
Figure 21.
1 F
0.1 F
0.1 F
AD9802